Abstract: Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created.

Abstract: A method of determining overlay of a patterning process, the method including: obtaining a detected representation of radiation redirected by one or more physical instances of a unit cell, wherein the unit cell has geometric symmetry at a nominal value of overlay and wherein the detected representation of the radiation was obtained by illuminating a substrate with a radiation beam such that a beam spot on the substrate was filled with the one or more physical instances of the unit cell; and determining, from optical characteristic values from the detected radiation representation, a value of a first overlay for the unit cell separately from a second overlay for the unit cell that is also obtainable from the same optical characteristic values, wherein the first overlay is in a different direction than the second overlay or between a different combination of parts of the unit cell than the second overlay.

Abstract: A battery pack receives a charging current from a charger via a power line. The battery pack includes a battery management unit and a transmitting unit. The battery management unit is coupled to a plurality of battery cells and is operable for acquiring data associated with the battery pack. The transmitting unit is coupled to the battery management unit and is operable for transmitting the data to the charger via a power line.

Abstract: A computer-aided method for configuring a hardware verification system is presented. The method includes receiving, by the computer, a first data representative of a first design of an integrated circuit, when the computer is invoked to configure the verification system, and transforming, using the computer, the first data into a second data representative of a second design. The second design includes a functionality of the first design, and a first circuit adapted to compute a third data representative of a power consumption of a first portion of the first design when the hardware verification system is configured with the second data and run. The first circuit is programmable without reconfiguring the second design.

Abstract: A customizable routing system allows designers to create custom connection layouts that can be stored, turned into templates, reused, and further customized. The system describes designer-input custom connection layouts in terms of “structural directives” that specify its patterns and properties instead of using precise dimensions. Structural directives may describe particular connection patterns between structural components (e.g., backbone or fishbone), the placement, width, direction or layer of specific structural components, and properties of structural components relative to other components. These structural directives are implemented generally during routing, such as through design constraints, which allows the router to locally optimize the design (e.g., for cost or wire length) while considering the structural intentions of the designer.

Abstract: A method for visualizing a performance distribution of an integrated circuit (IC) design is provided. The method includes determining a yield limit based on a group of Monte Carlo simulations of the IC design, and a functional yield, and selecting an initial yield based on an initial specification value from the group of Monte Carlo simulations. The method also includes selecting additional yield values based on additional specification values and on the group of Monte Carlo simulations of the IC design, wherein the low yield values are estimated using Kernel Density Estimation, and the high yield values are estimated using repeated binary search. The cumulative distribution function and probability density function for a performance of the IC design are estimated based on the additional yield values and the additional specification values. Also, the method includes obtaining a quantile representation for the performance of the IC design from the cumulative distribution function.

Abstract: This application discloses performing functional verification on a circuit design describing an electronic device and a computing system to determine occurrences of coverpoints and coverage crosses within a covergroup based on the results of the functional verification of the circuit design. Each coverpoint corresponds to a signal state or a variable value in the circuit design during the functional verification. Each of the coverage crosses corresponds to a different plurality of the coverpoints occurring concurrently. The computing system can generate a graphical presentation of the covergroup. The graphical presentation include nodes, each of which corresponding to the coverpoints or the coverage crosses. The nodes can be arranged in the graphical presentation based on connectivity between the coverpoints and the coverage crosses and clustered in the graphical presentation based on the occurrences of the coverpoints and coverage crosses during the functional verification of the circuit design.

Abstract: In accordance with aspects of the present invention, a wireless power integrated circuit is presented. The wireless power integrated circuit includes a wireless power receiver circuit; a battery charger circuit; and a microprocessor coupled to control the wireless power receiver and the battery charger circuit.

Abstract: The disclosure relates to a method, apparatus and system to wirelessly charge a device without creating fire hazard or other risks to nearby sensitive objects. An exemplary embodiment includes a memory circuitry and a chipset. The chipset communicates with the memory circuitry and is configured to selectively communicate with one of a wireless charging module and an NFC module to detect presence of the sensitive device. The chipset can be further configured to: transmit a first polling signal at a first power level for a first duration and detect a response from the sensitive device; if no response is detected during the first duration, transmit a second polling signal at a second power level for a second duration; cease polling signal transmission if response is received to either the first or the second polling signals; and engage the wireless charging module to charge the proximally located wireless device if no response is detected from the sensitive device during the first or the second duration.

Abstract: Disclosed are techniques for implementing routing aware floorplanning or placement for an electronic design. These techniques preprocess an electronic design and a plurality of inputs for a floorplanner or placer, identify a tentative location for inserting a block comprising one or more pins into a floorplan or placement layout, snap the block to a legal location based at least in part upon one or more characteristics of the one or more pins or one or more pseudo-pins, and update the floorplan or placement layout with one or more geometric routes based in part or in whole upon the legal location.

Abstract: Aspects of the disclosed technology include a method including extracting, by a processor, a plurality of features from one from among a layout of a circuit, a netlist of the circuit, and the layout and the netlist of the circuit; computing, by the processor, respective lifetime distributions of the plurality of extracted features based on at least one circuit profile; and estimating, by the processor, a lifetime of the circuit by combining the respective lifetime distributions of the plurality of extracted features.

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), the layout comprising a resistor-capacitor (RC) netlist comprising a plurality of circuit nodes; identifying an RC network in the RC netlist; determining a characterization matrix corresponding to the RC network; updating the RC netlist by replacing the RC network with the characterization matrix; and calculating voltages and currents of the plurality of circuit nodes based on the updated RC netlist.

Abstract: A system-on-a-chip (SoC) includes a master module and a first adapter module. The master module includes an upstream interface and a downstream interface. The upstream interface is coupled to a host unit for receiving a write burst or a read burst therefrom. The master module is configured to convert the write burst or the read burst into a series of access requests to the downstream interface. The first adapter module includes an input interface, an output interface, and an endpoint interface, and an address Base Address Register (BAR). The input interface is coupled to the downstream interface of the master module. The output interface is coupled to a second adapter module or to a termination module. The endpoint interface is coupled to a first functional unit or to a third adapter module. The first adapter module is configured to detect a respective access request corresponding to the address BAR.

Abstract: A method of correcting a layout pattern is provided in the present invention. The method includes the following steps. A layout pattern including at least two adjacent rectangular sub patterns is provided. The layout pattern is then input into a computer system. An optical proximity correction including a bevel correction is then performed. The bevel correction includes forming a bevel at a corner of at least one of the two adjacent rectangular sub patterns, wherein the bevel is formed by chopping the corner, and moving the bevel toward an interaction of two neighboring segments of the bevel if a distance between the bevel and the other rectangular sub pattern is larger than a minimum value. The angle between a surface of the bevel and a surface of the rectangular sub pattern is not rectangular. The layout pattern is output to a mask after the optical proximity correction.

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), where the layout includes a plurality of patterns in one or more layers of the layout; performing a coloring operation; forming a list comprising at least one uncolorable cell group (UCG) of the layout based on a result of the coloring operation, where each of the at least one UCG comprises at least one uncolorable cell; and performing a first refinement for each UCG on the list. The first refinement is performed through: performing a movement on at least one uncolorable cell of the UCG; determining whether the UCG is colorable; and refining the layout by accepting the movement and removing the UCG from the list in response to the UCG being determined to be colorable.

Abstract: Layout simulation and verification of a semiconductor chip can require extensive design rule checking (DRC) and design rules for manufacturing (DRM) analysis of the design in order to ensure proper operation. DRC and DRM can be expensive in terms of computational time and resource usage. To mitigate some of the cost, a virtual layer can be constructed for a cell instance identified in the semiconductor design. Shapes including rectangles and polygons can be determined which traverse the cell instance and are from other hierarchical layers of the design. The shapes can be combined to generate a virtual layer used for simulation, validation, DRC, DRM, etc. The virtual layer can be augmented with traversing shape information from other instances of the cell. The rectangles, polygons, and complex polygons can be combined to simplify the virtual layer. Multiple virtual layers can be generated for the simulation and validation processes.

Abstract: Techniques are disclosed for aiding in charging an electronic device using a charging case. The charging case includes a conductive contact and may connect to a conductive contact of the electronic device while still allowing user access to the main connector port of the electronic device. The charging case includes a power module that may receive power from an external power source. The power module may include an inductive coupling coil, photovoltaic cells, or a power cable port. Circuitry within the charging case may control and transmit power from the power module to the electronic device through the conductive contacts. The charging case may include a battery. The charging case may also include a data module for receiving data from an external data source, and the case circuitry may process and transmit data from the data module to the electronic device through the conductive contacts.

Abstract: A computer implemented method is described for generating a layout of a circuit block of an integrated circuit. The method comprises receiving input data defining a logical operation of the circuit block, and accessing a cell library providing a plurality of cells that define circuit elements, in order to determine with reference to the input data the cells to be used to implement the circuit block. A place and route tool is then employed to generate the layout by determining a placement of the determined cells and performing a routing operation to determine routing paths to be provided within a plurality of metal layers in order to interconnect the determined cells. The cell library provides cells that define in at least one metal layer one or more superfluous metal sections that are required to comply with design rules but which are unused by the cell.

Abstract: A method of determining a parameter of a patterning process, the method including: obtaining a detected representation of radiation redirected by a structure having geometric symmetry at a nominal physical configuration, wherein the detected representation of the radiation was obtained by illuminating a substrate with a radiation beam such that a beam spot on the substrate was filled with the structure; and determining, by a hardware computer system, a value of the patterning process parameter based on optical characteristic values from an asymmetric optical characteristic distribution portion of the detected radiation representation with higher weight than another portion of the detected radiation representation, the asymmetric optical characteristic distribution arising from a different physical configuration of the structure than the nominal physical configuration.

Abstract: A wireless power transmission apparatus for high efficiency energy charging, includes a resonator configured to transmit power, and a power supply unit configured to supply power to the resonator. The apparatus further includes a first switching unit configured to connect the resonator to the power supply unit, and disconnect the resonator from the power supply unit, and a controller configured to control the first switching unit based on an amount of current flowing into the resonator.