Abstract: A method for applying approximate computing to internal circuits of a digital system is disclosed. The digital system is implemented on an LUT based reconfigurable device such as Field Programmable Gate Array (FPGA). The method includes generating a bit stream containing information regarding contents of a Look Up Table (LUT) and the connection between multiple LUTs. The method further includes generating an FPGA approximate design by implementing exact design using an FPGA design tool. Further, the method includes providing an input, the bit stream and FPGA design to a simulation tool. The method includes manipulating the bit stream to create an approximate design for reducing the dynamic power consumption of the digital system. The bit stream is manipulated by injecting/introducing an error on a single or multiple LUT or intermediate LUTs based on a theory of approximation while ensure that total error does not exceed the maximum possible error rate.

Abstract: A method and apparatus of a novel modeling scheme for performing optical lithography simulation for a multi-tone mask with a plurality of mask tones is described. The method generates a transmission function matrix based on a setting of the multi-tone mask. The method applies the transmission function matrix to transform a formula for calculating light intensity from Abbe's form to Hopkins' form while maintaining the accuracy of Abbe's form. The method then computes the light intensity using the transformed formula.

Abstract: Techniques for providing wired and wireless charging to a device are provided. An example of an apparatus for receiving power from a wired power supply and a wireless power supply according to the disclosure includes a wireless power receiver configured to receive power from the wireless power supply, a direct current input circuit configured to receive power from the wired power supply, a control circuit operably coupled to the wireless power receiver and the direct current input circuit and configured to determine a power transfer capability for each of the wired power supply and the wireless power supply, and select the wireless power receiver from the wireless power supply or with the direct current input circuit from the wired power supply to receive power based on the power transfer capabilities.

Abstract: A system, a computer program product, and method for physically fabricating an electronic circuit using design space exploration as part of a design process is described. The method begins with defining a plurality of design space parameters to be tuned along with parameter ranges for each of the plurality of design space parameters. Next an output target to be optimized is defined. A series of one or more test mask shapes are generated to appear on a photo mask using the plurality of design space parameters. A simulation of a post lithography or etch on the series of one or more test mask shapes is performed to produce simulation output values. Next, the simulation output values and corresponding design space parameters are fed into to a Bayesian inference algorithm for assessment and identification of a next combination of design space parameters to investigate.

Abstract: Systems and methods for power management are disclosed herein. In one disclosed embodiment, a battery charging system includes a battery charger for simultaneously charging a battery (and/or providing power to a system load) with multiple power sources, using a closed-loop charging servo target based on measurements taken by one or more gauges. In some embodiments, the multiple power sources may be utilized simultaneously according to a charging profile that specifies, e.g., one or more battery charging parameters, as well as according to determined priority levels for one or more of the multiple power sources coupled to the battery. In some embodiments, the priority level of a given power source is not fixed; rather, the priority level for the given power source may change based upon the characteristics of the given power source. In some embodiments, the priority levels for the multiple power sources are implemented using cascaded voltage target values.

Abstract: A computer executable tool analyzes Boolean logic in a gate-level netlist responsible for generating false Xs due to X-pessimism in logic simulation to produce a compact fix that corrects the X-pessimism problem. The fix restores logic simulation value from X to hardware-accurate non-X value and solves X-pessimism issues in logic simulation.

Abstract: A battery management system (BMS) used in a battery pack, the battery pack has a discharging switch coupled between a battery and a load, and the load has a capacitor charged by the battery pack. The BMS has a driver circuit having a power supply terminal to receive a drive voltage, a ground reference terminal coupled to receive the battery pack voltage and an output terminal coupled to a control terminal of the discharging switch. The BMS generates a normal drive voltage and a ramp drive voltage, and the normal drive voltage is selected as the drive voltage when the voltage difference between the battery voltage and the battery pack voltage is less than a threshold voltage, and the ramp drive voltage is selected as the drive voltage when the voltage difference between the battery voltage and the battery pack voltage is higher than the threshold voltage.

Abstract: A transformer less battery charger system. In one embodiment, the battery charger system includes input terminals for receiving an AC voltage, output terminals for receiving terminals of a rechargeable battery pack, and a non-isolated DC-DC converter coupled between the input terminals and the output terminals. A device is also coupled somewhere between the input terminals and the output terminals. The device is configured to selectively and indirectly couple the input terminals to the output terminals. More particularly, the device indirectly couples the input terminals to the output terminals when the rechargeable battery pack terminals are received by the output terminals, and the device indirectly decouples the input terminals from the output terminals when the rechargeable battery pack terminals are separated from the output terminals.

Abstract: This application discloses a computing system to perform one or more static checks on clock domain crossings in a circuit design to detect combinational logic configured to generate output signals having glitches that cross clock domains in a circuit design. The computing system can identify the combinational logic is configured to generate the output signal based, at least in part, on an input signal and an inversion of the input signal. The computing system can identify conditions that, when satisfied, allow the combinational logic to generate the output signal based, at least in part, on the input signal and the inversion of the input signal, and generate a glitch expression based, at least in part, on the identified conditions. The computing system can determine the combinational logic is configured to generate at least one glitch in the output signal based, at least in part, on the glitch expression.

Abstract: Provided is an integrated circuit. The integrated circuit includes: a first standard cell comprising a P-type Fin Field Effect Transistor (FinFET) region and an N-type FinFET region; and a filler cell adjacent to the first standard cell in a first direction and including a first region and a second region arranged in a second direction perpendicular to the first direction, wherein the first region includes a plurality of first insulating structures spaced apart from each other in the first direction, and the second region includes a second insulating structure having a width greater than that of at least one of the plurality of first insulating structures in the first direction, and one of the first region and the second region is arranged adjacent to the P-type FinFET region in the first direction and the other is arranged adjacent to the N-type FinFET region in the first direction.

Abstract: This application discloses a computing system to receive a specification of prototype wiring corresponding to a signal in a logical design of a wire harness, locate a section of a vehicle to include a portion of the wire harness corresponding to the signal in the logical design, and insert the prototype wiring into a physical design of the wire harness corresponding to the located section of the vehicle. The specification of the prototype wiring can identify a particular vehicle configuration and insert the prototype wiring into a physical design of the wire harness for the particular vehicle configuration. The computing system can receive constraints configured to control synthesis of the logical design into the physical design of the wire harness, and generate portions of the physical design of the wire harness based on the constraints, while retaining the prototype wiring that was inserted into the physical design.

Abstract: A method of configuring a parameter determination process, the method including: obtaining a mathematical model of a structure, the mathematical model configured to predict an optical response when illuminating the structure with a radiation beam and the structure having geometric symmetry at a nominal physical configuration; using, by a hardware computer system, the mathematical model to simulate a perturbation in the physical configuration of the structure of a certain amount to determine a corresponding change of the optical response in each of a plurality of pixels to obtain a plurality of pixel sensitivities; and based on the pixel sensitivities, determining a plurality of weights for combination with measured pixel optical characteristic values of the structure on a substrate to yield a value of a parameter associated with change in the physical configuration, each weight corresponding to a pixel.

Abstract: A charging device for charging an electric vehicle, the electric vehicle comprising at least one electrical energy consumer member and at least one energy storage member in order to enable the electric vehicle to travel within a transport space in which the charging device is located, the charging device being configured to charge the energy storage member of the electric vehicle, when the electric vehicle is proximate to the charging device, the charging device includes: an energy storage device; a voltage regulator; and a connection device; the connection device being configured to electrically connect the energy storage device of the charging device, via the voltage regulator, with the energy storage member of the electric vehicle and to transfer at least partially the electrical energy stored by the energy storage device of the charging device toward the energy storage member of the electric vehicle.

Abstract: A method of manufacturing an integrated circuit (IC) including instances of standard cells includes arranging a first instance and arranging a second instance adjacent to the first instance. The second instance has a front-end layer pattern corresponding to a context group of the first instance. The context group includes information about front-end layer patterns of instances, the front-end layer patterns causing a same local layout effect (LLE) on the first instance and arranged adjacent to the first instance.

Abstract: Methods and apparatus for wireless charging are provided. Transmission power transmitted from a wireless power transmitter is received at a power receiver of a wireless power receiver. A battery of the wireless power receiver is charged with the received transmission power. It is determined whether the battery is fully charged. A packet from a communication unit of the wireless power receiver is transmitted to the wireless power transmitter when the battery is fully charged. An auxiliary charge of the battery is performed by receiving strength-reduced transmission power from the wireless power transmitter.

Abstract: Techniques and a system for visualization or interaction with a quantum processor are provided. In one example, a system includes a quantum programming component and a visualization component. The quantum programming component manages a quantum programming process to generate topology data for a quantum processor that is indicative of a physical topology of a set of qubits associated with the quantum processor. The visualization component generates visualization data for the topology data that comprises a set of planar slice elements arranged to correspond to the physical topology of the set of qubits. The set of planar slice elements indicate one or more operations performed at a time step associated with the quantum programming process.

Abstract: A zinc-air cell, a battery which is a low weight, low volume, or higher energy system, or a combination thereof and an apparatus for recharging the same are disclosed.

Abstract: A method of modifying a cell includes identifying a maximum overlapped pin group. The method further includes determining a number of pins in the maximum overlapped pin group. The method further includes determining a span region of the maximum overlapped pin group. The method further includes comparing the number of pins and the span region to determine a global tolerance of the cell. The method further includes increasing a length of at least one pin of the maximum overlapped pin group in response to the global tolerance failing to satisfy a predetermined threshold. The method further includes fabricating a mask based on the increased length of the at least one pin.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to mask structures and methods of manufacture. The method includes determining a plane through a frontside surface and a backside surface of a mask, each plane representing a flatness of the frontside surface and the backside surface, respectively; subtracting, using at least one computing device, a difference between the plane of the frontside surface and the plane of the backside surface to find a thickness variation; generating, using the at least one computing device, a fitting to fit the thickness variation; and subtracting, using the at least one computing device, the fitting from the thickness variation to generate a residual structure for collecting a residual flatness measurement.

Abstract: In some examples, a system for modifying circuit can include a processor to detect a previous routed top level circuit design that was proven to close timing within a predetermined range and congestion below a threshold level. The processor can also detect a new pin to be added to a new circuit design and detect user input indicating a bounding box corresponding to a new macro boundary in the previous routed top level circuit design. Additionally, the processor can identify a location of a net in the previous circuit design corresponding to the new pin, wherein the new pin is placed at an intersection between the net and the bounding box. Furthermore, the processor can manufacture a circuit based on the previous circuit design and the placement of the new pin at the intersection between the net and the bounding box.