Abstract: A computer-implemented method for integrated circuit routing is described. The computer-implemented method comprising receiving a description of interconnected terminals of an integrated circuit with a wiring route electrically coupling the interconnected terminals and configuring a simulated environment defined via a plurality of voxels based on the description. The individual voxels included in the plurality of voxels each correspond to a spatial representation for a corresponding region of a layout associated with the integrated circuit. The computer-implemented method further includes determining local contributions of the individual voxels to a characteristic metric of the integrated circuit based on an electromagnetic simulation of the integrated circuit and revising the wiring route based on the local contributions of the individual voxels.

Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

Abstract: Various implementations described herein refer to a device having an integrated circuit with multiple tiers including a first tier and a second tier that are arranged vertically in a stacked configuration. The first tier may have first functional components, and the second tier may have second functional components. The device may have a three-dimensional (3D) connection within the first tier that allows for synchronous signaling between the first functional components and the second functional components for reducing latency between the multiple tiers including the first tier and the second tier.

Abstract: A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.

Abstract: A method for the exchange of electrical energy between at least two moving, electrically powered vehicles, comprising the steps: providing a first and a second electrically powered vehicle, having a respective electrical energy store, the energy store of the first and the second vehicle can emit or receive electrical energy, and the first and second vehicles move or are to be moved along a first or second route; changing the first and second routes in such a way that both changed routes coincide along a route section; steering the first and second vehicle along the changed first and second route in such a way that both the vehicles move along the coinciding route section at a distance to one another that is smaller than a predefined maximum distance; and transferring electrical energy from the energy store of the first vehicle to the energy store of the second vehicle.

Abstract: A method of routing a clock tree including a plurality of clock nets of an integrated circuit, where each of the plurality of clock nets includes at least one clock repeater, includes determining a level of a clock net of the plurality of clock nets based on a number of clock gating cells that a clock signal passes through until the clock net receives the clock signal from a clock source and routing a plurality of conductive lines in each of the plurality of clock nets by applying different routing rules to clock nets having different levels based on the determined level. Each of the plurality of clock nets is configured to transfer the clock signal to a plurality of synchronous elements or another clock net. The plurality of synchronous elements operate in synchronization with the clock signal and are included in the integrated circuit.

Abstract: A lithographic process is performed on a set of semiconductor substrates consisting of a plurality of substrates. As part of the process, the set of substrates is partitioned into a number of subsets. The partitioning may be based on a set of characteristics associated with a first layer on the substrates. A fingerprint of a performance parameter is then determined for at least one substrate of the set of substrates. Under some circumstances, the fingerprint is determined for one substrate of each subset of substrates. The fingerprint is associated with at least the first layer. A correction for the performance parameter associated with an application of a subsequent layer is then derived, the derivation being based on the determined fingerprint and the partitioning of the set of substrates.

Abstract: An apparatus for conductive charging has a vehicle part fixed on a vehicle and a fixed robot part movable relative to the vehicle part the parts being fittable together for charging. Respective sets of vehicle and robot contacts are provided in housing the robot and vehicle parts. The robot contacts in the robot part are recessed in the housing of the robot part and the vehicle contacts are nonmovably mounted in the housing of the vehicle part. A robot base carries the robot contacts of the robot part. A contact tab extends from the robot base. A vehicle base carries the contacts of the vehicle part and is formed by a plurality of base sections surrounding a cylindrical sleeve. A contact spring extends from between two of the base sections of the vehicle base.

Abstract: A layout method includes generating a design data comprising an electronic circuit, and generating a design layout by placing a first cell corresponding to the electronic circuit. The first cell includes a first source/drain region and a second source/drain region extending in a first direction in a first layer, a gate electrode extending in a second direction perpendicular to the first direction in a second layer, and a first conductive line arranged in a third layer over the second layer and electrically connected to one of the first source/drain region, the second source/drain region and the gate electrode. The first cell is defined by a left cell side and a right cell side. At least one of the left cell side, the right cell side, the gate electrode and the first conductive line extends in a third direction not parallel to the first and second directions.

Abstract: A calibration current load is selectively coupled to an output of a pulse frequency modulated (PFM) DC-DC converter during a calibration operation to increase charge supplied from a battery supplying an input voltage to the converter. A voltage across a sense resistor in series with the battery is integrated during a measurement interval while the calibration current load is coupled to the output. A charge drawn per pulse from the battery is determined based on the sense resistor, the integrated voltage and the number of pulses during the measurement interval. Alternatively, a first PFM frequency is determined with a first calibration current load coupled to the converter output. A second PFM frequency is determined with a second calibration current load. The charge drawn per pulse from the battery is determined based on the first and second PFM frequencies and the first and second calibration current loads.

Abstract: Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.

Abstract: A computer-implemented method, a system, and non-transitory computer-readable storage medium for designing electrical circuits are provided. In the method input data is received and processed to generate a representation of the electrical circuit. A first process is repeatedly performed to identify a plurality of candidate routes for connecting a first and second circuit element based on the representation. A candidate route is selected from the plurality of candidate routes based on a look ahead search. The first process includes selecting a first point in the representation, executing a second process to identify a set of candidate points, and selecting a second point from the set of candidate points. The second process comprises evaluating at least one candidate path extending in a linear direction from the first point to identify the set of candidate points based on at least a constraint and a topology of the electrical circuit.

Abstract: The invention relates to the field of electric vehicles, and particularly provides a direct-current charging gun and charging pile. The invention aims to solve the problem that a user, when operating a current direct-current charging gun, needs to make round trips back and forth between a charging pile and a charging gun to stop charging, pull out the gun and return the gun, thereby degrading the user experience.

Abstract: A system includes an automatic charging device. The automatic charging device includes a movable arm configured to connect a charging plug head in electric communication with a vehicle inlet of an electric vehicle. The system includes a current detector configured to be in electrical communication with the automatic charging device.

Abstract: This application discloses a computing system to identify net lines corresponding to connections between pins of a source layout design describing a first electronic device and pins of a target layout design describing a second electronic device, scan the net lines in an order selected based, at least in part, on an orientation of the net lines between pins of the source layout design and the pins of the target layout design, identify a plurality of the scanned net lines cross each other, and unravel the crossed net lines by swapping pin assignments of the crossed net lines. The computing system can implement a machine learning algorithm having a first stage to determine a scan order for the net lines and having a second stage to identify the net lines that cross each other and unravel the crossed net lines.

Abstract: A method and apparatus are disclosed for a Battery Management System (BMS) for the controlling of the charging and discharging of a plurality of battery cells (12). Each battery cell has an associated plurality of control circuits (32, 36) which monitor and control the charging of individual battery cells. These units are controlled by a central microcontroller (14) which shunts current around the battery cell if fully charged and stops discharge if a battery cell is fully discharged in order to prevent damage to the other cells.

Abstract: Various embodiments of the present invention relate to an electronic device for diagnosing a battery, and the electronic device may include a battery; and a power management module operatively connected with the battery, and including a charging circuit which controls charge of the battery, wherein the power management module is configured to monitor a charge state of the battery, if the battery reaches a first designated state, identify a time taken to change from the first designated state to a second designated state, and determine whether the battery is abnormal, based at least in part on the identified time. Other various embodiments are possible.

Abstract: A circuit includes a first transistor, a second type-one transistor, a first type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor. Third type-one transistor has a second active-region and a gate conductively connected to each other. The fifth type-one transistor has a first active-region conductively connected with the gate of the third type-one transistor and has a second active-region configured to have a first supply voltage of a second power supply. The fifth type-one transistor is configured to be at a conducting state.

Abstract: A optical proximity effect correction method includes: fabricating a test pattern mask according to design rules of a target pattern; obtaining data required by an optical proximity effect correction model, and establishing the optical proximity effect correction model; obtaining line end shortening data of the test pattern, and establishing a line end shortening rule table; determining an initial correction value according to the line end shortening rule table; and correcting the target pattern according to the initial correction value and the optical proximity effect correction model.

Abstract: Systems and methods for designing a robotic system architecture are disclosed. The methods include generating a model that defines one or more requirements for a robotic device for a mapping between a software graph and a hardware graph. The model is used for allocating a plurality of computational tasks in a computational path included in the software graph to a plurality of hardware components of the robotic device to yield a robotic system architecture. The methods also include using the robotic system architecture to configure the robotic device to be capable of performing functions corresponding to the software graph, where the robotic system architecture is optimized to meet one or more latency requirements.