Abstract: A storage system, a storage node, and a data storage method are provided. The storage system includes a plurality of computing nodes and a plurality of storage nodes, and each storage node includes a hard disk. A client writes to-be-stored data into a memory of a first computing node, and writes a log of the to-be-stored data into storage space corresponding to a first access address of a first storage node. This implements storage of the to-be-stored data.

Abstract: Methods, systems, and devices for improved implicit ordered command handling are described. For instance, a memory device may receive, from a host device, a first command and a second command. The memory device may determine whether a first memory operation associated with the first command and a second memory operation associated with the second command are to be performed in an order relative to each other based on a first time when the first command is received relative to a second time when the second command is received. The memory device may select whether to perform a first memory access procedure or a second memory access procedure based on whether the first memory operation and the second memory operation are a same type of memory operation and on whether the first memory operation and the second memory operation are to be performed in the order relative to each other.

Abstract: A storage module includes a set of memories. Each of the memories in the set of memories may be divided into a set of portions. A controller is configured to transfer data between the set of memories and a host connected through an interface. A set of channels connects the set of memories to the controller. The controller is also configured to select: a memory from the set of memories, a portion from the set of portions for the selected memory, and/or a channel from the set of channels, e.g., connected to the selected memory, based upon an identification (ID) associated with the data. The ID may be separate from the data and a write address of the data, and the selected memory, the selected portion, and the selected channel may be used to store the data.

Abstract: Read Quality of Service in a solid state drive is improved by allowing a host system communicatively coupled to the solid state drive to control garbage collection in the solid state drive. Through the use of controlled garbage collection, the host system can control when to start and stop garbage collection in the solid state drive and the number of NAND dies engaged in garbage-collection operations.

Abstract: A memory system controls timing of a refresh operation. The memory system includes a non-volatile memory including first and second memory cell units and a controller connectable to a host. The controller stores an execution time of write and erase operations with respect to the first memory cell unit, receives from the host power-on time information indicating a power-on time of the memory system when the memory system is powered on, determines a first time period from a last write or erase operation with respect to the first memory cell unit based on the stored execution time and the power-on time, determines an execution time of the refresh operation of transferring data stored in the first memory cell unit to the second memory cell unit based on the first time period, and starts the refresh operation at the determined execution time.

Abstract: A computer system may include a processor; a first memory device; a second memory device; a cache memory including a plurality of cache entries and a cache controller. The cache controller is configured to manage a flag indicating whether a caching data is provided from the first memory device or the second memory device. The cache controller determines a cache entry to be evicted from the cache entries based on a cache miss ratio and a cache occupancy ratio.

Abstract: A method, apparatus, electronic device and storage medium for data caching based on data popularity is provided. In the method, first access data transmitted by at least one client is received. The first access data represents an instruction log of a remote direct data read instruction transmitted by the client for target data cached in a non-uniform memory access structure. A data popularity of the target data is obtained based on the first access data. The data popularity represents a frequency of the target data accessed by the remote direct data read instruction. Based on the data popularity of the target data, the target data is cached to a target location in a data storage unit implemented based on the non-uniform memory access structure. Alternatively, the target data out of the data storage unit is migrated. The target location has a data read-write speed corresponding to the data popularity.

Abstract: An apparatus illustratively comprises at least one processing device that comprises a processor coupled to a memory. The at least one processing device is configured to maintain in a host device queue depth measures for respective paths over which input-output operations are delivered from the host device to a storage system, and to control path selection for delivery of additional input-output operations from the host device to the storage system based at least in part on the queue depth measures maintained for the paths. The at least one processing device may comprise at least one multi-path input-output driver of the host device, with maintaining the queue depth measures and controlling the path selection being performed at least in part by the at least one multi-path input-output driver of the host device. The multi-path input-output driver illustratively comprises a lockless polled-mode driver implemented in a user space of the host device.

Abstract: A first user-initiated data write request including stream data is received from an edge device executing in a first zone. The stream data is partitioned into at least one segment and an event included in the stream data is written into the at least one segment based on an event's routing key. A segment container of a segment store hosts the at least one segment. The stream data is transmitted to a tier-1 storage of the first zone in order to provide a low-latency access to the stream data for the first user. Thereafter, the stream data is moved to a tier-2 storage of a second zone for permanent storage of the stream data. When requested by a second user operating in the second zone, a read-only version of the segment container retrieves the stream data from the tier-2 storage.

Abstract: A method for performing data access management of a memory device in predetermined communications architecture with aid of unbalanced table update size and associated apparatus are provided. The memory device may be arranged to receive a set of first commands, receive a set of first data with a first active block according to the set of first commands, and update a temporary physical-to-logical (P2L) address mapping table corresponding to the first active block, and determine a selected table update size among multiple predetermined table update sizes such as multiple table entry counts and update at least one logical-to-physical address mapping table according to a set of P2L table entries corresponding to the selected table update size in the temporary P2L address mapping table, where the table update size may be dynamically changed for enhancing overall performance.

Abstract: A system includes a memory device associated with a logical address space, and a processing device, operatively coupled to the memory device. The processing device can provide, to a host system, usable capacity information and supported logical address granularity information for the logical address space. The processing device can obtain, from the host system, a logical address granularity configuration for a partition of the logical address space. The processing device can provide, to the host system, an acknowledgement of receipt of the logical address granularity configuration.

Abstract: Techniques are described herein that are capable of performing pointer-based sharing of a data structure between threads. A process, including first and second threads, is executed. A first memory system associated with the first thread is created to manage a first memory page that points to a shared array buffer that includes a data structure stored in contiguous memory spaces. A second memory system associated with the second thread is created to manage a second memory page that points to the shared array buffer. The second thread is configured to have access to the data structure in the shared array buffer by causing a pointer, pointing to the data structure, and a size indicator, indicating a size of the data structure, to be sent from the first thread to the second thread. The data structure is capable of being changed without being re-arranged to be contiguous in memory.

Abstract: A memory system includes a memory controller and a memory device including a plurality of dies, each die including a plurality of blocks. A plurality of commands are configured to control the memory device in units of super blocks. During a first time interval, a first erase operation is performed on a first-first block among the first-first block to a first-Mth block, and a first program operation is performed on a second-first block to a second-Mth block, based on the first commands. During a second time interval, a second erase operation is performed on a first-second block among the first-first block to the first-Mth block, and a second program operation is performed on the first-first block and one or more blocks among the second-first block to the second-Mth block, based on the second commands.

Abstract: A CXL memory module, a memory data swap method and a computer system. The CXL memory module may include a flash memory chip, a memory chip, and a controller chip connected with the flash memory chip and the memory chip. The controller chip is configured to be able to swap a part of data in the memory chip into the flash memory chip.

Abstract: Memory access control in a virtualization environment is provided. Sets of page tables are maintained, with each set corresponding to a given hypervisor application and guest virtual machine (VM), and each set including mappings to a subset of the guest VM memory to thereby limit an amount of the quest VM memory that is accessible Presentation of these sets is controlled to present just one of the sets at any given time for hypervisor processing to access guest VM memory.

Abstract: An apparatus in an illustrative embodiment implements a proxy device for a first logical storage device. The proxy device inserts tags into respective received input-output (IO) operations before directing those IO operations to the first logical storage device. The apparatus further implements a mirror device to provide a mirroring arrangement between the proxy device and a second logical storage device. In addition, the apparatus checks, in an entry point associated with the first logical storage device, each IO operation directed to the first logical storage device for a tag inserted by the proxy device. The apparatus provides, from the entry point to the first logical storage device, any received IO operations that have the tag. Furthermore, the apparatus redirects, from the entry point to the mirror device providing the mirroring arrangement, any received IO operations that do not have the tag.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a memory reliability value associated with an individual portion of the set of memory components and selects a partition closing time for the individual portion of the set of memory components based on the memory reliability value. The controller defines a partition of the individual portion of the set of memory components based on the partition closing time and associates the partition with a bin of a plurality of bins, each of the plurality of bins representing an individual read level threshold voltage against which a charge distribution of data stored in the individual portion of the set of memory components is compared to determine one or more logical values.

Abstract: Systems and methods for analyzing memory architectures and for mapping data structures in software programs to appropriate memory to take advantage of the different memory architectures. A computer architecture having a processor connected to one or more first memories and one or more second memories is defined, wherein the first memories and the second memories are characterized by different performance profiles. An executable of a software program is instrumented to capture, during runtime, patterns of access to selected data structures of the executable. Based on an analysis of the patterns of access, allocation of the selected data structures between the first and second memories is determined.

Abstract: Various implementations described herein relate to systems and methods for a storage device (e.g., a Solid State Drive (SSD)) to perform a Compute Function (CF). One or more embodiments include a method by which a data transfer is annotated to call out a computation to be performed by the storage device on data before, after, or in parallel with reading the data from or writing the data to the storage device. One or more embodiments include a storage device including a controller, wherein the controller is configured to perform a method including receiving a command from a host, the command identifying the CF, and in response to receiving the command, performing the CF on at least one of internal data stored in the storage device or external data transferred from the host to determine the computation result of the CF.

Abstract: A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, a non-volatile memory, and a controller. The controller is configured to receive a read command to read a data word from an address of the array and decode the address to generate a decoded address. The controller is further configured to retrieve response data from the decoded address of the array, retrieve a location indicia corresponding to the decoded address from the non-volatile memory, and verify that the location indicia corresponds to the address. The controller can optionally be further configured to indicate an error if the location indicia does not correspond to the address.