Abstract: An apparatus in an illustrative embodiment implements a proxy device for a first logical storage device. The proxy device inserts tags into respective received input-output (IO) operations before directing those IO operations to the first logical storage device. The apparatus further implements a mirror device to provide a mirroring arrangement between the proxy device and a second logical storage device. In addition, the apparatus checks, in an entry point associated with the first logical storage device, each IO operation directed to the first logical storage device for a tag inserted by the proxy device. The apparatus provides, from the entry point to the first logical storage device, any received IO operations that have the tag. Furthermore, the apparatus redirects, from the entry point to the mirror device providing the mirroring arrangement, any received IO operations that do not have the tag.

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a memory reliability value associated with an individual portion of the set of memory components and selects a partition closing time for the individual portion of the set of memory components based on the memory reliability value. The controller defines a partition of the individual portion of the set of memory components based on the partition closing time and associates the partition with a bin of a plurality of bins, each of the plurality of bins representing an individual read level threshold voltage against which a charge distribution of data stored in the individual portion of the set of memory components is compared to determine one or more logical values.

Abstract: Systems and methods for analyzing memory architectures and for mapping data structures in software programs to appropriate memory to take advantage of the different memory architectures. A computer architecture having a processor connected to one or more first memories and one or more second memories is defined, wherein the first memories and the second memories are characterized by different performance profiles. An executable of a software program is instrumented to capture, during runtime, patterns of access to selected data structures of the executable. Based on an analysis of the patterns of access, allocation of the selected data structures between the first and second memories is determined.

Abstract: Various implementations described herein relate to systems and methods for a storage device (e.g., a Solid State Drive (SSD)) to perform a Compute Function (CF). One or more embodiments include a method by which a data transfer is annotated to call out a computation to be performed by the storage device on data before, after, or in parallel with reading the data from or writing the data to the storage device. One or more embodiments include a storage device including a controller, wherein the controller is configured to perform a method including receiving a command from a host, the command identifying the CF, and in response to receiving the command, performing the CF on at least one of internal data stored in the storage device or external data transferred from the host to determine the computation result of the CF.

Abstract: Aspects of a storage device including a memory and a controller are provided. The memory includes a plurality of non-volatile memory packages coupled to the switch, with each non-volatile memory package including a plurality of non-volatile memory dies. The controller monitors a wear level of each non-volatile memory package in the plurality of non-volatile memory packages connected to the controller via the switch. The controller determines whether a wear level of a first non-volatile memory package of the plurality of non-volatile memory packages exceeds a wear level threshold. The controller also can transfer data from the first non-volatile memory package to a second non-volatile memory package of the plurality of non-volatile memory packages through the switch based on the wear level of the first non-volatile memory package exceeding the wear level threshold. Thus, the controller may facilitate a persistent switch-based storage controller, thereby improving memory capacity of the storage device.

Abstract: A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, a non-volatile memory, and a controller. The controller is configured to receive a read command to read a data word from an address of the array and decode the address to generate a decoded address. The controller is further configured to retrieve response data from the decoded address of the array, retrieve a location indicia corresponding to the decoded address from the non-volatile memory, and verify that the location indicia corresponds to the address. The controller can optionally be further configured to indicate an error if the location indicia does not correspond to the address.

Abstract: A data storage device in accordance with an embodiment may include a controller and a memory device. The controller is configured to output a read control signal including an option number related to a read condition. The memory device is configured to perform a read operation based on a read condition corresponding to the option number in response to the read control signal. The read condition for the option number is configured to be stored in a read condition table storage circuit included in the memory device.

Abstract: Example implementations relate to virtual persistent volumes. In an example, a virtual persistent volume storage class is presented to a container orchestrator that includes parameters describing an associated virtual storage policy. In response to a provisioning request that identifies the virtual persistent volume storage class, a virtual persistent volume is created by determining a mapping of the parameters of the virtual persistent volume storage class to parameters of available storage classes so that the parameters of the virtual persistent volume storage class are fulfilled. At least one volume is provisioned to constitute the virtual persistent volume, according to the mapping.

Abstract: A processing system employs a method to order the elements within a memory. Ordering the elements includes receiving an accessed memory element. The accessed memory element is requested by a processor from a memory. Further, the accessed memory element is compared to stored elements within the memory to generate control signals. Gate control signals from the control signals are generated. The order of the stored elements within the memory is updated based on the gate control signals.

Abstract: A method for adaptively managing data disk capacity can automatically adjust an available capacity of a group of data disks based on a capacity value of a data disk whose capacity is the smallest in the group of data disks and a capacity difference threshold. In the method, the available capacity of the group of data disks may be automatically adjusted based on the new capacity of the smallest capacity disk, in response to the capacity of the smallest capacity disk in the group of data disks is changed.

Abstract: A system includes a reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric. The reconfigurable dataflow processor can be configured to execute a plurality of tensor indexing expressions and access the array of memory units according to a memory unit partitioning solution.

Abstract: An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

Abstract: Systems and methods are disclosed for enabling a memory sub-system to perform firmware-based monitoring of system state information without adding latency to the memory sub-system. The memory sub-system controller can include multiple CPUs which can be employed to perform different tasks. The memory sub-system controller can employ one of the frontend CPUs as a monitoring CPU capable of executing a data-gathering task to retrieve system state information from another CPU.

Abstract: A storage device that includes a nonvolatile memory device is described. The storage device includes areas and a controller. The controller receives a write command and data from an external host device. The controller then preferentially writes the data in an area associated with a turbo write based on a turbo write policy, or in an area not associated with a turbo write based on a normal write policy. The controller also receives a move command from the external host device and moves data stored in the area to a different area based on the move command.

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.

Abstract: Methods, and computer program product for writing data sets to and from cloud storage for legacy mainframe applications. A call to a mount request issued by the operating system is intercepted. An exit call to prepare for dataset write is received from an OS open routine. At least one call to a Basic Sequential Access Method (BSAM) End of Block (EOB) write routine is intercepted. Subject to the at least one call to the BSAM EOB routine being associated with cloud storage, data chunks are sent in an asynchronous manner to cloud storage. A second exit call for finalizing writing of the data chunks to the cloud storage is received. A call to an unmount request is intercepted. As a result, data is written directly from the mainframe to the cloud storage without intermediate storage.

Abstract: Methods, systems, and devices for using a completion flag for memory operations are described. A completion flag for a memory device may indicate whether at least one access operation has been completed at the memory device. A controller may poll the completion flag, and if the completion flag indicates that at least one access operation has been completed at the memory device, the controller may poll a status register for the memory device to obtain additional information regarding one or more completed access operations at the memory device.

Abstract: Methods, systems, and devices for read latency and suspend modes are described. A memory system may operate in a first mode of operation associated with a first set of access operations including executing read operations, executing write operations, and suspending write operations. The memory system may receive, from a host system, an indication to switch to a second mode of operation associated with a decreased latency for executing write operations based on limiting a suspension of write operations. For example, the host system may transmit a command including the indication to switch to the second mode of operation. In another example, the host system may write a value to a register at the memory system including the indication to switch to the second mode of operation. Based on receiving the indication from the host system, the memory system may then operate according to the second mode of operation.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to exemplary embodiments of the present disclosure, the memory system may calibrate a history read bias until a termination condition is satisfied based on a number of error bits generated in a first read operation. The memory system may reduce the overhead incurred in handling errors that occur during a read operation by reducing the number of error bits that can occur during read operation due to non-optimization of the history read bias value.

Abstract: A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is “hybrid” in that it combines a cache of relatively fast, durable, and expensive memory (e.g. DRAM) with a larger amount of relatively slow, wear-sensitive, and inexpensive memory (e.g. flash). A hybrid controller component services memory commands from the memory controller component and additionally manages cache fetch and evict operations that keep the cache populated with instructions and data that have a high degree of locality of reference. The memory controller alerts the hybrid controller of available access slots to the cache so that the hybrid controller can use the available access slots for cache fetch and evict operations with minimal interference to the memory controller.