Abstract: Rather than use one long folding operation to fold data from single-level cell (SLC) blocks into a multi-level cell (MLC) block, a storage system uses a multi-stage folding operation. By breaking up the folding process into stages, SLC blocks involved in an earlier stage can be released prior to a subsequent stage being performed. This can increase performance of the storage system by releasing SLC source blocks sooner and reducing an SLC block budget requirement.

Abstract: Apparatus, method, and system for efficiently identifying and tracking cold memory pages are disclosed. The apparatus in one embodiment includes one or more processor cores to access memory pages stored in the memory by issuing access requests to the memory and a page index bitmap to track accesses made by the one or more processor cores to the memory pages. The tracked accesses are usable to identify infrequently-accessed memory pages, where the infrequently-accessed memory pages are removed from the memory and stored in a secondary storage.

Abstract: A cache system having cache sets, and the cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system also has a control register and a mapping circuit coupled to the control register to map respective physical outputs of the cache sets to a first logical cache and a second logical cache according to a state of the control register. The first logical cache can be a normal or main cache for non-speculative executions by a processor and the second logical cache can be a shadow cache for speculative executions by the processor.

Abstract: Provided are a computational storage system, computational storage processor, solid-state drive (SSD) and data storing method. The method may include receiving a first storing instruction based on a storage object, generating a second storing instruction based on a flash memory address according to information carried by the first storing instruction and SSD resource information maintained locally, and sending the generated second storing instruction to the SSD. The SSD resource information may include resource occupation information in the SSD. Generating the second storing instruction may include parsing an identification of a storage object, data length information and a starting source address of entire data, allocating a flash memory address or addresses in one or more SSDs for storing data of the storage object according to the data length information and the resource occupancy information in the SSD, and generating the second storing instructions for each SSD.

Abstract: A storage device includes a non-volatile memory including memory blocks, and a storage controller including a history buffer including plural history read level storage areas corresponding to the memory blocks. The storage controller dynamically adjusts a number of the history read level storage areas allocated to one or more of the plurality of memory blocks based on reliabilities of the memory blocks during runtime of the storage device. The storage controller increases a number of history read level storage areas allocated to a first memory block among the memory blocks that has a relatively low reliability with respect to the reliabilities of remaining ones of the memory blocks.

Abstract: Mechanisms for reducing memory inconsistencies between two synchronized computing devices are provided. A first hypervisor module of a first computing device iteratively determines that content of a memory page of a plurality of memory pages has been modified. The content of the memory page is sent to a second hypervisor module on a second computing device. At least one other memory page of the plurality of memory pages is identified, and a verification value based on the content of the at least one other memory page is generated. The verification value and a memory page identifier that identifies the at least one other memory page is sent to the second hypervisor module on the second computing device.

Abstract: A current cycle count associated with a memory sub-system is determined. The current cycle count is compared to a set of cycle count threshold levels to determine a current lifecycle stage of the memory sub-system. A temperature associated with the memory sub-system is measured. The temperature is compared to a set of temperature levels to determine a current temperature level of the memory sub-system. A write-to-read delay time corresponding to the current lifecycle stage and the current temperature level is determined.

Abstract: An operation method of a UFS device including: determining, by a host, area information for write data, wherein in a turbo read the write data is stored in a non-pinned or pinned buffer area and in a normal read the write data is stored in a user storage; transferring, by the host, a first command UFS protocol information unit (UPIU); transferring, by the UFS device, an RTT UPIU to the host, transferring, by the host, a DATA OUT UPIU to the UFS device; mapping, by UFS device, a first logical block address with a physical address of an area corresponding to the area information; transferring, by the host, a second command UPIU; and performing the turbo read on the area to read data corresponding to the first logical block address when the area corresponding to the area information is the pinned or non-pinned turbo write buffer.

Abstract: A message that includes a queue identifier (ID) is received from a first hardware functional module. A virtual queue is selected from a plurality of virtual queues in a shared queue structure based at least in part on the queue ID and configurable message handling settings(s). The message is stored in the selected virtual queue and a message recipient is selected from a plurality of potential message recipients based at least in part on the configurable message handling setting(s), where the plurality of potential message recipients includes the second hardware functional module and the processor module. The message is provided to the selected message recipient.

Abstract: Example embodiments employ a selective memory swapping system for selectively placing non-volatile memory devices of a computer system offline, e.g., for background updating, and online, for use by a computer system, whereby the background updating process includes a mechanism for performing forensics analysis and updating of offline memory devices while an alternate memory device is usable by a user of the first computer system.

Abstract: A request to perform a data operation associated with at least one memory unit in a plurality of memory units of a memory device is received. The at least one memory unit includes a first group of memory cells, each memory cell supporting a specified number of charge levels such that each memory cell having the specified charge level represents a non-integer number of bits. The first group of memory cells represents a first sequence of bits based on a first sequence of charge levels formed by the first group of memory cells. The data operation is performed with respect to the at least one memory unit based on a mapping stored on the system. The mapping assigns an individual sequence of charge levels from an individual group cell to an individual sequence of bits represented by the individual group of memory cells.

Abstract: A host sends a storage system a command to read data from a memory and then a command to write the data back to the memory to defragment the data. The host sends flags along with the commands. The flag sent with the read command causes the storage system to take a snapshot of the logical-to-physical address map relevant to the data. The flag sent with the write command causes the storage system to compare the snapshot with the current version of the logical-to-physical address map and write the data back to the memory only if there is a match.

Abstract: Techniques are disclosed relating to provisioning fault domain sets (FDS). In some embodiments, a computer server system implements an FDS for disseminating a storage service across a plurality of fault domains. To implement the FDS, in some embodiments, the computer server system access FDS data specifying a desired state of the FDS in which the storage service is disseminated across at least a particular number of fault domains. The computer server system may determine available resources of the plurality of fault domains and determine a current state of the FDS based on fault domains that have already been provisioned to the FDS. Based on at least the desired state of the FDS, the current state of the FDS, and the available resources, the computer server system provisions one or more additional fault domains to the FDS to reconcile the FDS's current state with the FDS's desired state.

Abstract: One embodiment provides a method, including: receiving, at a central system, a query requesting access to a dataset, wherein the central system communicates with a plurality of data storage locations, each having a governance policy for data stored at the data storage location, wherein different portions of the dataset are stored within different of the plurality of data storage locations; sending a sub-query formulated based upon the query; receiving a governance enforcement actions listing corresponding to the portion of the dataset stored within the corresponding data storage location; generating a meta-policy of enforcement actions for all of the plurality of data storage locations storing portions of the dataset, wherein the meta-policy identifies enforcement actions and an order of the enforcement actions to be applied to the dataset; and providing the meta-policy to each of the plurality of data storage locations.

Abstract: The present disclosure includes apparatuses and methods related to a memory system with cache line data. An example apparatus can store data in a number of cache lines in the cache, wherein each of the number of lines includes a number of chunks of data that are individually accessible.

Abstract: A storage module includes a set of memories. Each of the memories in the set of memories may be divided into a set of portions. A controller is configured to transfer data between the set of memories and a host connected through an interface. A set of channels connects the set of memories to the controller. The controller is also configured to select: a memory from the set of memories, a portion from the set of portions for the selected memory, and/or a channel from the set of channels, e.g., connected to the selected memory, based upon an identification (ID) associated with the data. The ID may be separate from the data and a write address of the data, and the selected memory, the selected portion, and the selected channel may be used to store the data.

Abstract: A method for managing system resources includes receiving, by a storage device, a Quality of Service (QOS) parameter from a host. The storage device selects a first index type, from among index types, for a first index based on the QoS parameter and a computational load metric. The index types include one index type having an index structure that is a tree structure, a list structure, or a hash structure. The index structure is different from an index structure of another index type of the index types. The storage device sends feedback to the host regarding the first index type for the host to use in identifying a second index type for a second index to manage a computational load. The storage device accesses the data using the first index based on a processing of the user request, by the host, using the second index.

Abstract: The invention introduces a method for handling sudden power off recovery, performed by a processing unit of an electronic apparatus, to include: driving a flash interface to program data sent by a host into pseudo single-level cell (pSLC) blocks of multiple logical unit numbers (LUNs) in a single-level cell (SLC) mode with multiple channels after detecting that the electronic apparatus has suffered a sudden power off (SPO), and driving the flash interface to erase memory cells of all the pSLC blocks when data of all pSLC blocks has been read by the host. The pSLC blocks are reserved from being written to in regular operations until the SPO is detected.

Abstract: A memory system includes a host device including a host controller, and a memory device including a device controller and a non-volatile storage including a purge region and a memory region. The device controller communicates purge information associated with the purge region and including size information of the purge region. The host controller communicates a request for generating a first partition for a first logical unit in the memory region, and communicates a request for generating a second partition for a second logical unit in the purge region in response to the size information of the purge region.

Abstract: A method for storage cluster expansion is provided. The method includes distributing user data throughout a storage cluster as directed by each of a plurality of authorities in the storage cluster. Each of the plurality of authorities has a plurality of wards, and each of the plurality of wards has ownership of a range of the user data. The method includes splitting one of the plurality of authorities, as a parent authority, into at least two child authorities and assigning a first subset of the plurality of wards of the parent authority to one of the at least two child authorities, and a second subset of the plurality of wards of the parent authority to another one of the at least two child authorities.