Patents Examined by Nicholas A. Paperno
  • Patent number: 11797211
    Abstract: A method for storage cluster expansion is provided. The method includes distributing user data throughout a storage cluster as directed by each of a plurality of authorities in the storage cluster. Each of the plurality of authorities has a plurality of wards, and each of the plurality of wards has ownership of a range of the user data. The method includes splitting one of the plurality of authorities, as a parent authority, into at least two child authorities and assigning a first subset of the plurality of wards of the parent authority to one of the at least two child authorities, and a second subset of the plurality of wards of the parent authority to another one of the at least two child authorities.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: October 24, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Robert Lee, John Martin Hayes, Faissal Sleiman
  • Patent number: 11797200
    Abstract: A provided a storage device configured to support a number of namespaces. The storage device includes a memory and a controller coupled to the memory. The controller includes a host interface layer and a flash translation layer configured to report to the host interface layer a first over-provisioning chunk from an over-provisioning pool and a first chunk separate from the over-provisioning pool. The controller is configured to receive a command at the host interface layer to utilize a portion of the memory for a first namespace from among the number of namespaces and the first namespace includes an unaligned chunk. The controller is configured to utilize the first over-provisioning chunk as the unaligned chunk of the first namespace. A number of over-provisioning chunks to be utilized as unaligned chunks is less than the number of namespaces.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: October 24, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xiang Lian, Chao Yang
  • Patent number: 11784946
    Abstract: A processor, processor implementation method, and a storage medium are disclosed, which relates to the field of artificial intelligence and deep learning. The processor includes: a system controller a data packing and unpacking module, a storage array module, and an operation module configured to perform operation processing on the acquired first packet, generate the second packet according to the operation result data, and return the second packet to the data packing and unpacking module. The storage array module comprises N1 storage units. The data packing and unpacking module comprises N2 data packing and unpacking units, each of the data packing and unpacking units is connected to the routing and switching module through a data channel. The universal operation module comprises M operation units. The activation operation module comprises P operation unit, each of the operation units is connected to the routing and switching module through a data channel.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: October 10, 2023
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
    Inventor: Xiaoping Yan
  • Patent number: 11755242
    Abstract: A data merging method can copy a new logical to physical mapping table and update a copied logical to physical mapping table according to a physical address of a recycling unit expected to be written at the same time. In this way, the number of times that the same logic to physical mapping table is read multiple times during the data merging operation can be reduced to improve the execution efficiency of the data merging operation, thereby increasing the system performance of the memory storage device.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: September 12, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Che-Yueh Kuo, Li Hsun Lien
  • Patent number: 11747983
    Abstract: In various embodiments, a write state application generates a snapshot that includes one or more data values associated with a source dataset. In operation, the write state application performs one or more compression operations on the source dataset to generate a first compressed record. The write state application then serializes the first compressed record and a second compressed record to generate a first compressed record list. Finally, the write state application generates the snapshot based on the first compressed record list. When the data values are accessed from the first snapshot, the size of the snapshot is maintained. Advantageously, because the size of the snapshot is smaller than the size of the source dataset, some consumers that are unable to store the entire source dataset in random access memory (RAM) are able to store the entire snapshot in RAM.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: September 5, 2023
    Assignee: NETFLIX, INC.
    Inventor: John Andrew Koszewnik
  • Patent number: 11743209
    Abstract: A processor, processor implementation method, and a storage medium are disclosed, which relates to the field of artificial intelligence and deep learning. The processor includes: a system controller a data packing and unpacking module, a storage array module, and an operation module configured to perform operation processing on the acquired first packet, generate the second packet according to the operation result data, and return the second packet to the data packing and unpacking module. The storage array module comprises N1 storage units. The data packing and unpacking module comprises N2 data packing and unpacking units, each of the data packing and unpacking units is connected to the routing and switching module through a data channel. The universal operation module comprises M operation units. The activation operation module comprises P operation unit, each of the operation units is connected to the routing and switching module through a data channel.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: August 29, 2023
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.
    Inventor: Xiaoping Yan
  • Patent number: 11709611
    Abstract: A system includes a parser that receives and parses source code for a reconfigurable dataflow processor, a tensor expression extractor configured to extract tensor indexing expressions from the source code, a logical memory constraint generator that converts the tensor indexing expressions to logical memory indexing constraints, a grouping module that groups the logical memory indexing constraints into concurrent access groups and a memory partitioning module that determines a memory unit partitioning solution for each concurrent access group. The system also includes reconfigurable dataflow processor that comprises an array of compute units and an array of memory units interconnected with a switching fabric. The reconfigurable dataflow processor may be configured to execute the plurality of tensor indexing expressions and access the array of memory units according to the memory unit partitioning solution. A corresponding method and computer-readable medium are also disclosed herein.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: July 25, 2023
    Assignee: SambaNova Systems, Inc.
    Inventors: Matthew S. Feldman, Yaqi Zhang
  • Patent number: 11704050
    Abstract: A memory system which stores a journal including mapping change information, either in a first memory area or a second memory area, depending on available space of a memory device included in the memory system, being greater than a threshold.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: July 18, 2023
    Assignee: SK hynix Inc.
    Inventors: Jin Pyo Kim, Woo Young Yang
  • Patent number: 11693586
    Abstract: The present disclosure relates to designating or allocating static and dynamic SLC blocks between a non-write burst free block pool and a write burst free block pool. In some embodiments, a free block pool can be utilized by a host for write burst operations and/or non-write burst operations. In these embodiments, the over provisioning portion of the memory sub-system can be designated into a plurality of portions.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: July 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Jianmin Huang
  • Patent number: 11687254
    Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data (and CRC) and does not transmit control signals, over its communications link with the data buffer circuits. In one aspect, the memory control circuit does not send the store data tag to the data buffer circuits. In one embodiment, the Host and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, e.g., local store tag FIFO, which contains the same tags in the same sequence. A periodic system check and resynchronization method is also disclosed.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: June 27, 2023
    Assignee: International Business Machines Corporation
    Inventors: Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
  • Patent number: 11675527
    Abstract: A memory system may include: a nonvolatile memory device suitable for storing user data and meta data of the user data; and a controller suitable for uploading at least some of the meta data to a host. When the size of a free space of a storage space of the host, allocated to store the uploaded meta data, is equal to or less than a preset value, the controller may upload hot meta data to the host according to the number of normal read requests received from the host and the ratio of the normal read requests.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: June 13, 2023
    Assignee: SK hynix Inc.
    Inventor: Kwang Su Kim
  • Patent number: 11675528
    Abstract: Aspects of a storage device including a memory and a controller are provided. The memory includes a plurality of non-volatile memory packages coupled to the switch, in which each non-volatile memory package includes a plurality of non-volatile memory dies. The controller can select a non-volatile memory package with the switch. The controller can establish a data channel connection between the selected non-volatile memory package and the controller via the switch. In some aspects, the selected non-volatile memory package is transitioned into an active mode and one or more non-selected non-volatile memory packages are each transitioned into a standby mode. The controller also can perform one or more storage device operations with one or more non-volatile memory dies of the plurality of non-volatile memory dies within the selected non-volatile memory package. Thus, the controller may facilitate a switch based ball grid array extension, thereby improving memory capacity of the storage device.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: June 13, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Akhilesh Yadav, Ramanathan Muthiah, Eldhose Peter
  • Patent number: 11669264
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The non-volatile memory is configured to store an address translation table and a data map. In a case where an invalidation command for invalidating the data written in the non-volatile memory is received from the host, the controller is configured to update the address translation table and the data map based on the invalidation command. A response to the invalidation command is transmitted to the host after the address translation table is updated and before the data map is updated.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: June 6, 2023
    Assignee: Kioxia Corporation
    Inventors: Yuki Sasaki, Shinichi Kanno
  • Patent number: 11663140
    Abstract: A memory device and methods for operating the same are provided. The memory device includes an array of memory cells, a non-volatile memory, and a controller. The controller is configured to receive a read command to read a data word from an address of the array and decode the address to generate a decoded address. The controller is further configured to retrieve response data from the decoded address of the array, retrieve a location indicia corresponding to the decoded address from the non-volatile memory, and verify that the location indicia corresponds to the address. The controller can optionally be further configured to indicate an error if the location indicia does not correspond to the address.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: May 30, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Alberto Troia
  • Patent number: 11662935
    Abstract: Methods, systems, and devices for improved data management for memory are described. An apparatus may include a memory array including one or more blocks of memory cells. Data read from a block of memory cells may be written to a buffer, to support providing the data to a host system or modification of the data by the host system. If a quantity of read commands performed at the block of memory cells satisfies a threshold, the data may be written from the buffer to a different block of memory cells, rather than the block from which the data was previously read.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: May 30, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Luigi Esposito, Alberto Sassara, Paolo Papa, Massimo Iaculo
  • Patent number: 11650748
    Abstract: In a method for offloading data processing into computational storage, a request to offload data computation into computational storage is received. One or more transactions to encapsulate the request are prepared. One or more write requests are generated based on the one or more transactions, and the one or more transactions are stored into one or more journals. A set of transactions is extracted from the one or more journals. A subset of the set of transactions is received at an eBPF subsystem, where the subset corresponds to one or more computation requests. Information from a file is extracted, where the information corresponds to one or more logical block addresses (LBAs). The one or more computation requests are performed on the one or more LBAs using the subset of the set of transactions, and an indication corresponding to the performed computation requests is generated.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: May 16, 2023
    Assignees: Lemon Inc., Beijing Youzhuju Network Technology Co Ltd.
    Inventors: Viacheslav Dubeyko, Jian Wang
  • Patent number: 11650938
    Abstract: A device-capability-based locking key management system includes a key management system coupled to a server device via a network. The server device includes storage devices coupled to a remote access controller device. The remote access controller device identifies each of the storage devices, and then identifies a key management profile for each of the storage devices. A first key management profile identified for at least one first storage device is different from a second key management profile identified for at least one second storage device. The remote access controller device then uses the respective key management profile identified for each of the storage devices to create a respective key management sub-client for each of the storage devices, and each respective key management sub-client communicates with the key management system to provide a locking key for its respective storage device.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: May 16, 2023
    Assignee: Dell Products L.P.
    Inventors: Rama Rao Bisa, Sushma Basavarajaiah, Mukund P. Khatri, Chandrashekar Nelogal, Chitrak Gupta, Manjunath Am
  • Patent number: 11650753
    Abstract: In response to receiving an exception indication, an exception-handling state variable in state information is asserted. Firmware instruction(s) are selected from a plurality of firmware instructions based at least in part on: (1) a conditions table that includes condition(s) for handling the plurality of firmware instructions and (2) the state information that includes the exception-handling state variable. It is determined how to handle the selected firmware instruction(s) based at least in part on: (1) the conditions table and (2) the state information that includes the exception-handling state variable where. The plurality of firmware instructions includes: (1) a non-exception-handling set of firmware instruction(s) and (2) an exception-handling set of firmware instruction(s).
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: May 16, 2023
    Inventors: Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Wanqiang Zhang
  • Patent number: 11650737
    Abstract: A computer-implemented method comprises initializing a plurality of segment lists. Each segment list of the plurality of segment lists corresponds to a respective one of a plurality of disk drives. Each segment list divides storage space of the respective disk drive into a plurality of segments. The method further comprises, for each of the plurality of disk drives, identifying one or more candidate segments from the plurality of segments; calculating a respective segment distance variance for one or more combinations of identified candidate segments. Each combination of identified candidate segments includes one candidate segment for each of the plurality of disk drives. The method further comprises selecting a combination of the one or more combinations of identified candidate segments having the smallest respective segment distance variance; and storing data on the plurality of disk drives according to the selected combination of identified candidate segments.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: May 16, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lin Feng Shen, Ji Dong Li, Yong Zheng, Guang Han Sui, Shuo Feng, Hai Zhong Zhou, Yu Bing Tang, Wu Xu
  • Patent number: 11645003
    Abstract: According to one embodiment, a memory system includes a non-volatile memory, and a controller configured to control the non-volatile memory. The controller is configured to write data to the non-volatile memory, read the written data from the non-volatile memory after writing of the data is completed, generate parity data corresponding to the read data, and write the generated parity data to a memory for parity storage.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: May 9, 2023
    Assignee: Kioxia Corporation
    Inventors: Atsushi Okamoto, Tetsuya Yasuda, Akinori Nagaoka