Abstract: Log processing provides a status message of a storage node cluster is obtained by a first node. The status message marks a master storage node of the storage node cluster. The first node can send a first write operation request to the master storage node based on the status message so that the master storage node agrees on a first write operation after agreeing on a received log with a slave storage node in the storage node cluster. The first node receives a feedback message sent after the master storage node agrees on the first write operation with the slave storage node in the storage node cluster. The feedback message includes identification information and a response to the first write operation request. The first node can send to the master storage node a target message including a current iteration identifier, and the master storage node can use the current iteration identifier to determine whether the target message is from a latest master compute node.

Abstract: One or more aspects of the present disclosure relate to allocating virtual memory to one or more virtual machines (VMs). The one or more VMs can be established by a hypervisor of a storage device. The virtual memory can be allocated to the established one or more VMs. The virtual memory can correspond to non-volatile (NV) memory of a global memory of the storage device.

Abstract: A memory device includes a first nonvolatile memory including a resistive memory cell; and a controller. The controller may be configured to provide the first nonvolatile memory with a first data, a first program command, and a first address. The controller may be configured to receive a second data, which is a verify read from the resistive memory cell programmed with the first data, from the first nonvolatile memory in response to the first program command. The controller may be configured to compare the first data with the second data to detect a number of fail cells. When the number of detected fail cells is greater than a reference value, the controller may be configured to generate a third data obtained by inversing the first data, and provide the third data to the first nonvolatile memory. The first data may include an inversion flag bit.

Abstract: Example embodiments employ a selective memory swapping system for selectively placing non-volatile memory devices of a computer system offline, e.g., for background updating, and online, for use by a computer system, whereby the background updating process includes a mechanism for performing forensics analysis and updating of offline memory devices while an alternate memory device is usable by a user of the first computer system.

Abstract: Devices and techniques for communicating a programmable atomic operator to a memory controller are described herein. A memory controller can receive a memory request and extract a command indicator that indicates a programmable atomic operator (PAO) command from the memory request. The memory controller can then extract a PAO index from the request and invoke the PAO based on the PAO index.

Abstract: A control apparatus configured to record data in a recording medium includes a cluster management unit configured to manage clusters in a predetermined area in a recording area of the recording medium, a recording management unit configured to manage clusters in the predetermined area in recording units each having a predetermined size larger than each cluster size, and a directory cluster allocation unit configured to set a cluster in the predetermined area to a directory cluster in which a directory is recorded. The directory cluster allocation unit is configured to allocate a cluster out of clusters in a tail end area in the predetermined area to the directory cluster, the clusters in the tail end area being smaller than a size of the recording units having the predetermined size and being not managed by the recording management unit.

Abstract: Systems, apparatuses, and methods for dynamically adjusting cache policies to reduce execution core wait time are disclosed. A processor includes a cache subsystem. The cache subsystem includes one or more cache levels and one or more cache controllers. A cache controller partitions a cache level into two test portions and a remainder portion. The cache controller applies a first policy to the first test portion and applies a second policy to the second test portion. The cache controller determines the amount of time the execution core spends waiting on accesses to the first and second test portions. If the measured wait time is less for the first test portion than for the second test portion, then the cache controller applies the first policy to the remainder portion. Otherwise, the cache controller applies the second policy to the remainder portion.

Abstract: A method and system for cache-based flow of a simple copy command is disclosed. The present disclosure generally relates to methods and systems for executing a simple copy command in a manner that mitigates additional latency in the device. According to certain embodiments, a copy command manager that includes one or more copy command slots is provided. When a simple copy command is received from a host, a copy command slot is allocated to the command, and the simple copy command is copied into the copy command slot. Upon copying the simple copy command to the copy command slot, an overlap table of the data storage device controller is updated to indicate the copy has been completed, and the completion is posted to the host. After posting, the simple copy command is carried out in the background through completion.

Abstract: A first operating characteristic and a second operating characteristic of a memory sub-system are determined. A write-to-read delay time is set in view of the first operating characteristic and the second operating characteristic. A read operation associated with a memory unit is executed following a period of at least the write-to-read delay time from a time of an execution of a write operation associated with the memory unit.

Abstract: A memory system determines a level of a read voltage, which is used for reading or recognizing data stored in non-volatile memory cells, in response to a change of a threshold voltage distribution which gradually widens due to charge loss or charge transfer in the non-volatile memory cells over time, so that it is possible to provide an apparatus and method which can avoid or reduce an error in a read operation.

Abstract: Techniques are disclosed relating to provisioning fault domain sets (FDS). In some embodiments, a computer server system implements an FDS for disseminating a storage service across a plurality of fault domains. To implement the FDS, in some embodiments, the computer server system access FDS data specifying a desired state of the FDS in which the storage service is disseminated across at least a particular number of fault domains. The computer server system may determine available resources of the plurality of fault domains and determine a current state of the FDS based on fault domains that have already been provisioned to the FDS. Based on at least the desired state of the FDS, the current state of the FDS, and the available resources, the computer server system provisions one or more additional fault domains to the FDS to reconcile the FDS's current state with the FDS's desired state.

Abstract: A storage device that includes a nonvolatile memory device is described. The storage device includes areas and a controller. The controller receives a write command and data from an external host device. The controller then preferentially writes the data in an area associated with a turbo write based on a turbo write policy, or in an area not associated with a turbo write based on a normal write policy. The controller also receives a move command from the external host device and moves data stored in the area to a different area based on the move command.

Abstract: A storage device including: a nonvolatile memory device including a first, second and third area; and a controller to receive a first write command including a first logical block address from a host, to receive first data corresponding to the first logical block address in response to the first write command, and store the first data in the nonvolatile memory device, when the first write command includes area information, the controller stores the first data in the first area or the second area based on the area information, when the first write command does not include the area information, the controller stores the first data in the third area, each of the first area and the second area includes memory cells each storing “n” bits (n being a positive integer), and the third area includes memory cells each storing “m” bits (m being a positive integer greater than n).

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in memory of the computer system. In one approach, access to memory in an address space is maintained by an operating system of the computer system. A virtual page is associated with a first memory type. A page table entry is generated to map a virtual address of the virtual page to a physical address in a first memory device of the first memory type. The page table entry is used by a memory management unit to store the virtual page at the physical address.

Abstract: Systems and methods for optimizing the internal metadata management of key-value solid state drives (KVSSDs) are provided. A key-to-physical-address (K2P) mapping scheme (resizable hash-based indexing) that focuses on index resizing and space optimization can be used. The resizable metadata management scheme can efficiently handle a highly variable workload in an incredibly large keyspace. It can provide predictable metadata access cost, as well as fast membership checking. The metadata management structure can be designed to ensure near-constant performance in terms of metadata access cost and fast membership checking.

Abstract: A non-volatile memory express (NVMe)-based data read method, apparatus, and system are provided. In various embodiments, a read instruction can be triggered by a host. The read instruction carries indication information of a first address opened by the host to an NVMe controller for addressing and accessing. In those embodiments, the host after obtaining the read instruction can send a data packet to the host. The data packet carries the first address and payload data. Still in those embodiments, the host can, after receiving the data packet, determine a second address based on the first address, and store the payload data into storage space indicated by the second address. The second address may be a private memory address of the host. Because a relationship between the second address and a communication protocol is broken, and the host may access the second address without being restricted by the communication protocol.

Abstract: A method for storage cluster expansion is provided. The method includes distributing user data throughout a storage cluster as directed by each of a plurality of authorities in the storage cluster. Each of the plurality of authorities has a plurality of wards, and each of the plurality of wards has ownership of a range of the user data. The method includes splitting one of the plurality of authorities, as a parent authority, into at least two child authorities and assigning a first subset of the plurality of wards of the parent authority to one of the at least two child authorities, and a second subset of the plurality of wards of the parent authority to another one of the at least two child authorities.

Abstract: computer-based system and method for selecting a write unit size for a block storage device, includes performing a plurality of sequences of I/O operations to the block storage device, each sequence having a write unit size from a plurality of write unit sizes; collecting performance metrics of the sequences of I/O operations; and selecting the write unit size for the block storage device from the plurality of write unit sizes based on the performance metrics. In some cases, preconditioning is performed prior to performing the plurality of sequences of I/O operations by emptying the block storage device; and writing data to the block storage device to fill the block storage device above a predetermined level.

Abstract: One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.