Abstract: Small objects are efficiently stored with erasure codes by combining a small object with other small objects and/or large objects to form a single large object for chunking, and providing early notification of permanent storage to the sources of the objects to prevent small objects from becoming stale while waiting for additional objects to be combined.

Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines processing on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission.

Abstract: In one aspect, a method includes making a first active buffer a passive buffer, generating a second active buffer to receive new I/Os, making a list of locations that need realignment in the passive buffer, flushing open I/Os at a splitter, reading I/Os which need realignment, discarding re-aligned I/Os for overwritten areas and sending the passive buffer to a replica site.

Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

Abstract: First in, first out (FIFO) memory queue architecture enabling a plurality of writers and a single reader to use the queue without mutual exclusive locking. The FIFO queue is implemented using an array. A write counter value associated with the array provides a reservation value to each writer that is mutually exclusive of the value provided to every other writer. A read counter value associated with the array prevents writers from writing over data messages stored in the array that are yet to be read by the single reader.

Abstract: A method for sharing a file between multiple operating systems on a probable electronic device is provided. The method includes the following steps: in a first operating system, a central processing unit storing a modified file into a memory of a shared access area; the central processing unit establishing a link relationship between the first operating system and a second operating system, so that the second operating system learns an address of the modified file stored in the memory of the shared access area; switching from the first operating system to the second operating system; and in the second operating system, the central processing unit accessing the modified file in the memory of the shared access area according to the link relationship.

Abstract: A storage device that maps logical addresses to physical addresses includes a memory that stores machine instructions and a processor coupled to the memory that executes the machine instructions to store a compressed mapping table in the memory. The compressed mapping table correlates logical addresses to locations in a storage. The storage device also stores a bundle of uncompressed mapping table entries starting at a first location in a cache and maps a first logical address associated with the uncompressed mapping table entry to the first location.

Abstract: Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. A processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to at least one of i) a determination that the local processor has no transaction, and ii) a determination that the prefetch request does not conflict with a transaction by providing a requested prefetch data by providing a requested prefetch data. A processor responds to a determination that the prefetch request conflicts with a transaction by suppressing a processing of the prefetch request.

Abstract: Embodiments are directed to a method of optimizing disk striping input/output (I/O) operations to an array of storage devices, by identifying an I/O request as a full stripe write request that stripes data across a plurality of storage devices of the array, converting the full stripe write request to a SCSI command block (CDB), and putting the SCSI command block in one of a stripe cache or a non-stripe cache that comprises a sorted linked list where each node of the linked list is a link to one of the plurality of storage devices.

Abstract: Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. A processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to at least one of i) a determination that the local processor has no transaction, and ii) a determination that the prefetch request does not conflict with a transaction by providing a requested prefetch data by providing a requested prefetch data. A processor responds to a determination that the prefetch request conflicts with a transaction by suppressing a processing of the prefetch request.

Abstract: For each storage array in a storage system, a single value score indicative of the overall health of the respective storage array is calculated. Storage array health score may be tracked over time and used to identify storage arrays in need of maintenance. The storage array health score may be calculated as a composite of four component scores: physical component health, logical component health, Service Level Objective compliance and Best Practice Configuration Compliance. The physical component and logical component scores may be based on multiple different category health scores, and each category health score may be based on multiple instance health scores. Health scores may be used to identify remedial actions and predict health score increase as a result of remedial actions.

Abstract: Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at least one hardware processor core and a sectored dynamic random access (DRAM) cache coupled to the at least one hardware processor core.

Abstract: Performance tuning in a storage system that includes one or more storage devices, including: storing, by a primary controller of the storage system, data corresponding to one or more computer processes into one or more of the one or more storage devices, determining, by a secondary controller that is configured similarly to the primary controller, one or more utilization patterns of the data, and initiating, in dependence upon the one or more utilization patterns of the data, a modification to a manner in which the one or more computer processes access the data stored in the one or more storage devices.

Abstract: Apparatus and method for managing data in a hybrid data storage device. In some embodiments, a hybrid device has a hard disc drive (HDD) controller circuit coupled to non-volatile rotatable media and a solid state drive (SSD) controller circuit coupled to non-volatile solid state memory. A top level controller circuit directs a selected access command one of the HDD controller circuit or the SSD controller circuit responsive to a selected parameter associated with the selected access command. In a normal mode, the top level controller circuit directs a transfer of data between the host and the HDD controller circuit and handles host interface communications. In a tunneling mode, the top level controller circuit directly connects the HDD controller circuit to the host device. In this way, tunnel mode bypasses processing operations required by the top level controller circuit. Tunnel mode and normal mode may be selected on a command-by-command basis.

Abstract: An exposed Internet Small Computer System Interface (iSCSI) target of a backup repository is defined as a source of, and a storage volume to be recovered as a target of, a mirrored pair of storage resources. The iSCSI target represents a point-in-time backup snapshot. Data from the iSCSI target is synchronized to the storage volume. The mechanisms of the illustrated embodiments leverage iSCSI with Instant Restore to reduce a Recovery Time Objective (RTO) and provide a secure transport when recovering a volume over a WAN.

Abstract: An exposed Internet Small Computer System Interface (iSCSI) target of a backup repository is defined as a source of, and a storage volume to be recovered as a target of, a mirrored pair of storage resources. The iSCSI target represents a point-in-time backup snapshot. Data from the iSCSI target is synchronized to the storage volume. The mechanisms of the illustrated embodiments leverage iSCSI with Instant Restore to reduce a Recovery Time Objective (RTO) and provide a secure transport when recovering a volume over a WAN.

Abstract: Embodiments described herein are directed to systems and methods for ordering read sector data that has been returned from a hard disk controller out of order. For example, in typical storage systems, the firmware of the storage system and/or the host interface typically process read sectors in logical block address order. However, some of the data that is received may be received out of order. As such, the disk block hardware within the hard disk controller may accept these out of order sectors from the read channel and subsequently provide information that describes the available sectors that are in order to the firmware and/or the host interface.

Abstract: In an approach for resolving terminated transactions in a transactional memory environment, a processor initiates a hardware transaction in a computing environment, wherein the hardware transaction accesses a memory location, and wherein the hardware transaction includes a transaction begin indicator and a transaction end indicator. A processor detects a conflicting access of the memory location while executing the hardware transaction. A processor aborts the hardware transaction based on the conflicting access of the memory location. Hardware determines that the conflicting access of the memory location is a transient condition. A processor reinitiates the hardware transaction.

Abstract: A portable storage system. The portable storage system comprises a portable storage device having a flash memory element and a loss-prevention unit. The portable storage system further comprises Master and Slave proximity elements. One of the proximity elements is physically connected with the portable storage device, while the other is physically connected with the loss-prevention unit. The Master proximity element is configured to wirelessly determine the presence of the Slave proximity element within a predefined range.

Abstract: A method of erasing volatile memory requiring refreshment using refresh circuitry to maintain data storage, the method comprising controlling the refresh circuitry for preventing refreshment of the memory upon occurrence of a predefined event which would require erasure of data stored in the memory by a previous user, process, application or service. A computer readable medium encoded with processor executable instructions for execution by a processing unit for controlling a refresh circuitry connected to a volatile memory for preventing refreshment of the memory at the predefined event. A refresh circuitry adapted to be connected to a volatile memory requiring refreshment using the refresh circuitry to maintain data storage, the refresh circuitry being adapted to prevent the refreshment of the memory at the occurrence of the predefined event. A volatile memory comprising a refresh circuitry adapted to prevent the refreshment of the memory at the occurrence of the predefined event.