Abstract: In an approach for resolving terminated transactions in a transactional memory environment, a processor initiates a hardware transaction in a computing environment, wherein the hardware transaction accesses a memory location, and wherein the hardware transaction includes a transaction begin indicator and a transaction end indicator. A processor detects a conflicting access of the memory location while executing the hardware transaction. A processor aborts the hardware transaction based on the conflicting access of the memory location. Hardware determines that the conflicting access of the memory location is a transient condition. A processor reinitiates the hardware transaction.

Abstract: Methods and apparatuses to control cache line coherency are described. A processor may include a first core having a cache to store a cache line, a second core to send a request for the cache line from the first core, moving logic to cause a move of the cache line between the first core and a memory and to update a tag directory of the move, and cache line coherency logic to create a chain home in the tag directory from the request to cause the cache line to be sent from the tag directory to the second core. A method to control cache line coherency may include creating a chain home in a tag directory from a request for a cache line in a first processor core from a second processor core to cause the cache line to be sent from the tag directory to the second processor core.

Abstract: A storage control device includes a processor. The processor is configured to acquire a first size. The processor is configured to calculate, for each of a plurality of storage devices, a total size of first data stored in each of the plurality of storage devices. The first data satisfies a predetermined condition. The processor is configured to select the first data in an ascending order of the total size. A sum of the total size of the selected first data is the first size or less. The processor is configured to copy the selected first data from the plurality of storage devices to a first storage device different from the plurality of storage devices.

Abstract: System, method, and apparatus for integrated main memory (MM) and configurable coprocessor (CP) chip for processing subset of network functions. Chip supports external accesses to MM without additional latency from on-chip CP. On-chip memory scheduler resolves all bank conflicts and configurably load balances MM accesses. Instruction set and data on which the CP executes instructions are all disposed on-chip with no on-chip cache memory, thereby avoiding latency and coherency issues. Multiple independent and orthogonal threading domains used: a FIFO-based scheduling domain (SD) for the I/O; a multi-threaded processing domain for the CP. The CP is an array of independent, autonomous, unsequenced processing engines that process on-chip data tracked by SD of external CMD and reordered per FIFO CMD sequence before transmission.

Abstract: A processing device selectively backups only certain data based on a priority or binning structure. In one approach, a non-volatile logic controller stores the machine state by storing in non-volatile logic element arrays a portion of data representing the machine state less than all the data of the machine state. Accordingly, the non-volatile logic controller stores the machine state in the plurality of non-volatile logic element arrays by storing a first set of program data of the machine state according to a first category for backup and restoration and storing a second set of program data of the machine state according to a second category for backup and restoration.

Abstract: An information processing apparatus can prevent performance deterioration, and maintain fault tolerance, in a storage system having storage nodes of different capacities. The apparatus includes a data writing unit to divide received data into divided data, generate a parity data usable when re-configuring the received data having an error, and write divided data and parity data in storage nodes. The apparatus includes a relocation unit to assign a relocation position of the data based on a predetermined condition and store the data in the assigned storage nodes. The apparatus includes a data reading unit to read the divided data so as not to read parity data stored in the storage nodes by identifying the parity data.

Abstract: An intelligent electronic device (IED), e.g., an electrical power meter, having at least one removable memory device for storing data sensed and generated by the intelligent electronic device is provided. The IED includes a housing; at least one sensor; at least one analog-to-digital converter; at least one processing unit coupled to the at least one analog-to-digital converter configured to receive the digital data and store the digital data in a removable memory; and at least one device controller coupled to the at least one processing unit, the at least one device controller including an interface disposed on the housing for interfacing with the removable memory, wherein the at least one device controller is operative as a USB master or USB slave device controller.

Abstract: As a solution to the type of problems noted above, this disclosure provides novel methods and systems that include dual-port solid-state drive (SSD) DIMM devices to provide primary storage capabilities with very low latency and better availability of DDR4 devices. The dual-port DDR4-SSD flash memory devices guarantee primary storage devices still accessible with one CPU or network failure. The novel DDR4 memory bus devices may be used not only for memory media and storage device buffers, but also to allow two CPUs to share data stored in flash SSD chips and to greatly improve DDR4 bus efficiency and bus utilizations by block accesses and eliminate PCIE-DMA data transfers. Through the features of the claimed subject matter described herein, dual-port DDR4-DIMM memory devices can be achieved that provide an All-Flash-Array storage system with substantially higher reliability, availability, and performance over conventional SATA/SAS-SSD, PCIE-SSD, and NVME-SSD solutions.

Abstract: A data storage device is disclosed comprising a volatile memory, a primary and a secondary non-volatile memory (NVM), and control circuitry coupled to the volatile memory and the primary and secondary NVM and configured to write first data to the volatile memory, write the first data from the volatile memory to the secondary NVM before writing the first data to the primary NVM, attempt to write the first data to the primary NVM, wherein, during the attempt to write the first data to the primary NVM, after a portion of the first data has been successfully written to the primary NVM, a corresponding portion of the first data is released from the secondary NVM.

Abstract: A storage platform computing apparatus obtains a lifecycle management policy and configuration information for a cloud repository identified in the lifecycle management policy. The configuration information includes at least one access parameter for the cloud repository. The lifecycle management policy is applied to determine when an object is required to be replicated to the cloud repository in response to a received write request. A request to store the object in the cloud repository is generated, when the object is determined to be required to be stored in the cloud repository, wherein the request includes the access parameter. The request is sent to the cloud repository using a representational state transfer (REST) interface associated with the cloud repository.

Abstract: Techniques for backup and restore of optimized data streams are described. A chunk store includes each optimized data stream as a plurality of chunks including at least one data chunk and corresponding optimized stream metadata. The chunk store includes data chunks in a deduplicated manner. Optimized data streams stored in the chunk store are identified for backup. At least a portion of the chunk store is stored in backup storage according to an optimized backup technique, an un-optimized backup technique, an item level backup technique, or a data chunk identifier backup technique. Optimized data streams stored in the backup storage may be restored. A file reconstructor includes a callback module that generates calls to a restore application to request optimized stream metadata and any referenced data chunks from the backup storage. The file reconstructor reconstructs the data streams from the referenced data chunks.

Abstract: Technologies are generally described for methods and systems effective to access data in a cache. In an example, a method to access data in a cache may include processing a first request for data at a first memory address related to first data in a memory. The method may further include retrieving the first data from the memory. The method may further include storing the first data in a first cache line in the cache. The method may further include processing a second request for data at a second memory address related to second data in the memory. The method may further include retrieving the second data from the memory. The method may further include selecting a second cache line in the cache to store the second data based on the storage of the first data. The method may further include storing the second data in the second cache line.

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem adjusts access to the DRAM based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.

Abstract: A data storage system includes a pre-cache and a plurality of storage devices across which a data storage array is distributed. In response to receipt of a write request specifying a logical address and write data, the data storage system buffers the write request among a plurality of write requests in the pre-cache without provisioning in the data storage array a physical extent corresponding to the logical address. A management node analyzes the plurality of write requests buffered in the pre-cache. In response to the analyzing identifying a first pattern of write requests, the management node provisions, in the data storage array, a first physical extent having a smaller grain size and destages the write data to the first physical extent. In response to the analyzing identifying a second pattern of write requests, the management node provisions a second physical extent having a larger grain size and destages the write data from the pre-cache to the second physical extent.

Abstract: Systems, methods, and computer programs are disclosed for method for reducing memory subsystem power. In an exemplary method, a system resource manager provides memory performance requirements for a plurality of memory clients to a double data rate (DDR) subsystem. The DDR subsystem and the system resource manager reside on a system on chip (SoC) electrically coupled to a dynamic random access memory (DRAM). A cache hit rate is determined of each of the plurality of memory clients associated with a system cache residing on the DDR subsystem. The DDR subsystem controls a DDR clock frequency based on the memory performance requirements received from the system resource manager and the cache hit rates of the plurality of memory clients.

Abstract: In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.

Abstract: A Network Interface Device (NID) of a web hosting server implements multiple virtual NIDs. A virtual NID is configured by configuration information in an appropriate one of a set of smaller blocks in a high-speed memory on the NID. There is a smaller block for each virtual NID. A virtual machine on the host can configure its virtual NID by writing configuration information into a larger block in PCIe address space. Circuitry on the NID detects that the PCIe write is into address space occupied by the larger blocks. If the write is into this space, then address translation circuitry converts the PCIe address into a smaller address that maps to the appropriate one of the smaller blocks associated with the virtual NID to be configured. If the PCIe write is detected not to be an access of a larger block, then the NID does not perform the address translation.

Abstract: A method for processing data and an electronic device are provided. The method includes: assigning first and second address sets in relation to data to be stored in a memory, a predetermined address offset is defined between the first address set and the second address set; writing the data to the first address set in response to a data write command; and reading the data from the second address set in response to a data read command.

Abstract: A memory controller includes a state shaping encoder that receives k-bit write data, selects a logical page with reference to state shape mapping information, and changes data of the logical page to decrease an occurrence probability of a high-order program state among program states used to program the k-bit data in multi-level memory cells.

Abstract: Metadata that corresponds to application data is distributed across different disruption regions of an asymmetric memory component such that metadata is written in the same disruption region as the application data to which it corresponds. A first block of application data is written to a first disruption region and a second block of application data is written to a second disruption region. A first block of metadata corresponding to the first block of application data and a second block of metadata corresponding to the second block of application data both are generated. The first block of metadata is written to the first disruption region and the second block of metadata is written to the second disruption region such that the first and second blocks of metadata are written to the same disruption regions as the blocks of application data to which they correspond.