Abstract: A storage system having an input-output (IO) component, a solid state drive (SSD) with multiple logical units (LUNs), e.g., flash storage units, and a controller coupled to the IO component and the SSD. The controller can cause the storage system to receive an operation request, determine various operational throughputs associated with outstanding commands of the SSD (e.g., read or write commands to be performed by the SSD), determine a time required for the SSD to process the outstanding commands based in part on the operational throughputs, and assign a timeout value to the received operation request. The timeout value may correspond to the time required for the SSD to process the outstanding commands. Any of the operational throughputs may be throttled when a die temperature of any of the SSD's LUNs exceeds an operating temperature threshold, or when an ambient temperature affecting SSD exceeds an ambient temperature threshold.

Abstract: Systems and methods presented herein provide for region lock management in an expander. In one embodiment, an expander, being operable to link a plurality of initiators to a plurality of Redundant Array of Independent Disks logical volumes, includes a plurality of physical transceivers, each being operable to link the logical volumes to the initiators, and a region lock manager operable to receive a request from a first of the initiators to lock a region of the logical volumes for an input/output operation by the first initiator. The region lock manager is also operable to determine if the requested region is unlocked, to lock the requested region from the remaining initiators to allow the input/output operation of the first initiator after determining the requested region is unlocked, and to unlock the requested region after the input/output operation of the first initiator is complete.

Abstract: In at least some embodiments, a processor core executes a code segment including a memory transaction and a non-transactional memory access instructions preceding the memory transaction in program order. The memory transaction includes at least an initiating instruction, a transactional memory access instruction, and a terminating instruction. The initiating instruction has an implicit barrier that imparts the effect of ordering execution of the transactional memory access instruction within the memory transaction with respect to the non-transactional memory access instructions preceding the memory transaction in program order. Executing the code segment includes executing the transactional memory access instruction within the memory transaction concurrently with at least one of the non-transactional memory access instructions preceding the memory transaction in program order and enforcing the barrier implicit in the initiating instruction following execution of the initiating instruction.

Abstract: In at least some embodiments, a processor core executes a code segment including a memory transaction and a non-transactional memory access instructions preceding the memory transaction in program order. The memory transaction includes at least an initiating instruction, a transactional memory access instruction, and a terminating instruction. The initiating instruction has an implicit barrier that imparts the effect of ordering execution of the transactional memory access instruction within the memory transaction with respect to the non-transactional memory access instructions preceding the memory transaction in program order. Executing the code segment includes executing the transactional memory access instruction within the memory transaction concurrently with at least one of the non-transactional memory access instructions preceding the memory transaction in program order and enforcing the barrier implicit in the initiating instruction following execution of the initiating instruction.

Abstract: Memory lifetime extension for a data storage system having a first memory and a second memory includes determining a plurality of age-adjusted access values for a data block stored in the first memory based on access of the data block and at least one aging weight, determining an overall access value for the data block based on the plurality of age-adjusted access values, and determining if at least a portion of the data block should be stored in a cache memory of the second memory based on the overall access value. The at least one aging weight can be dynamically adjusted based on an expected remaining practical usable life of the second memory.

Abstract: A method begins by a dispersed storage (DS) processing obtaining estimated future availability information for storage units and organizing a plurality of sets of encoded data slices into a plurality of group-sets of encoded data slices. For each of the plurality of group-sets of encoded data slices, the method continues with the DS processing module estimating an approximate storage completion time to produce a plurality of approximate storage completion times. The method continues with the DS processing module establishing a time-availability pattern for writing the plurality of group-sets of encoded data slices to the storage units based on the estimated future availability information and the plurality of approximate storage completion times. The method continues with the DS processing module sending the plurality of group-sets of encoded data slices to at least some of the storage units for storage therein in accordance with the time-availability pattern.

Abstract: A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.

Abstract: A memory device according to an embodiment includes a non-volatile storage device, a volatile storage device that stores saved data which is saved in the host-side storage device when a first operation mode changing process is executed by the memory device, and a control unit. The control unit transmits, to the host device, a write command that is an instruction to write the saved data to the host-side storage device and the saved data, when the first operation mode changing process is executed by the memory device.

Abstract: A method for storing information may include determining whether a received data object fits inside a particular one of a plurality of free blocks in a memory bitmap. Each of the plurality of free blocks may include a column of the memory bitmap with a top margin, a bottom margin, and a predetermined width. If the received data object fits, the received data object may be stored in the particular one of the plurality of free blocks, starting at the margin of the particular one of the plurality of free blocks. The particular one of the plurality of data blocks may be resized by moving the margin to start below or next to the stored received data object. The determining may include, for each of the plurality of free blocks, a height of the received data object may be compared with a height of each of the free data blocks.

Abstract: A method includes, in a processor, processing program code that includes memory-access instructions, wherein at least some of the memory-access instructions include symbolic expressions that specify memory addresses in an external memory in terms of one or more register names. Based on respective formats of the memory addresses specified in the symbolic expressions, a sequence of load instructions that access a predictable pattern of memory addresses in the external memory is identified. At least one cache line that includes a plurality of data values is retrieved from the external memory. Based on the predictable pattern, two or more of the data values that are requested by respective load instructions in the sequence are saved from the cache line to the internal memory. The saved data values are assigned to be served from the internal memory to one or more instructions that depend on the respective load instructions.

Abstract: A method and apparatus for optimizing a backup chain using synthetic backups is described. In one embodiment, a method for creating synthetic incremental backups to optimize a backup chain comprises accessing a backup chain, which further comprises a plurality of incremental backups and determining schedule information defining a number of incremental backups to use to create one or more synthetic incremental backups representing the plurality of incremental backups from the backup chain, wherein the number of backups is defined by a numerical progression.

Abstract: A data storage system includes a higher level controller, a lower level controller, and a plurality of storage components including a particular storage component. Data is stored within the data storage system utilizing at least one level of striping across the plurality of storage components. Latencies of input/output operations (IOPs) requesting access to the data stored within the data storage system are monitored. In response to determining that a latency of a read IOP requesting read data stored in the particular storage component exceeds a latency threshold and in absence of a data error, the read IOP is serviced by reconstructing the read data from storage components among the plurality of storage components other than the particular storage component. The lower level controller also provides feedback to the higher level controller to cause the higher level controller to reduce IOPs directed to at least the particular storage component.

Abstract: A transactional memory receives a command, where the command includes an address and a novel DAT (Do Address Translation) bit. If the DAT bit is set and if the transactional memory is enabled to do address translations and if the command is for an access (read or write) of a memory of the transactional memory, then the transactional memory performs an address translation operation on the address of the command. Parameters of the address translation are programmable and are set up before the command is received. In one configuration, certain bits of the incoming address are deleted, and other bits are shifted in bit position, and a base address is ORed in, and a padding bit is added, thereby generating the translated address. The resulting translated address is then used to access the memory of the transactional memory to carry out the command.

Abstract: Example implementations of the present disclosure are directed to handling the eviction of a conflicting cuckoo entry while reducing performance degradation resulting. In example implementations, when an address is replacing another address, the evicted address does not necessarily map to the same places as the new address. Example implementations attempt to conduct a run through of the cache coherent directory with the new entry such that the evicted address can find an empty entry in the directory and fill the empty entry.

Abstract: Methods, apparatus and systems for memory access obscuration are provided. A first embodiment provides memory access obscuration in conjunction with deadlock avoidance. Such embodiment utilizes processor features including an instruction to enable monitoring of specified cache lines and an instruction that sets a status bit responsive to any foreign access (e.g., write or eviction due to a read) to the specified lines. A second embodiment provides memory access obscuration in conjunction with deadlock detection. Such embodiment utilizes the monitoring feature, as well as handler registration. A user-level handler may be asynchronously invoked responsive to a foreign write to any of the specified lines. Invocation of the handler more frequently than expected indicates that a deadlock may have been encountered. In such case, a deadlock policy may be enforced. Other embodiments are also described and claimed.

Abstract: The present invention relates to an apparatus and method for indicating flash memory life. While data is being stored in a flash memory, the number of writes in a plurality of blocks of the flash memory increases. The amount of flash memory life is calculated on the basis of the number of write times in the plurality of blocks. The calculated amount of life can be transmitted to a host. In addition, when the calculated amount of life is greater than a threshold value, a signal providing notice that the life of the flash memory has reached a dangerous level can be output.

Abstract: Provided are a method, system, and computer program product for determining a metric to use to determine whether to generate a low space alert. A determination is made of provisioned storage space comprising storage space allocated to at least one application, wherein applications may use less than all the provisioned storage space. A determination is made of available storage space comprising all installed storage space available for use by the at least one application having allocated storage space. A determination is made of allocated storage space comprising storage space used by the applications. A determination is made of an allocation metric as a function of the provisioned storage space, the allocated storage space, and the available storage space. The determined allocation metric is used to determine whether to generate a storage space related alert.

Abstract: A system that includes a storage drive and a controller communicatively coupled to the storage drive. The storage drive includes a first region of storage space that is mapped to a virtual volume and at least a second region of storage space reserved for over-provisioning operations. The controller is to unmap an operable portion of the first region of storage space in response to aging of the storage drive so that the unmapped portion can be used for over-provisioning operations.

Abstract: A memory card and a communication method between a memory card and a host unit are disclosed. High throughput of data between the memory card and the host unit is guaranteed by providing a communication interface between the memory card and the host unit including a first communication interface between a memory unit of the memory card and a control unit of the memory card and a second communication interface between the control unit of the memory card and the host unit.

Abstract: Embodiments of the invention are directed to optimizing reconstruction of operation data in volatile memory of solid-state storage subsystems. In various embodiments, operation data is stored in the volatile memory with persistent backup data of the operation data in the non-volatile memory. In one embodiment, operation data includes a superblock table that is used to identify most or all groups of blocks (superblocks) within the storage device that certain firmware components operate on. Sometimes operation data in the volatile memory is lost or corrupted due to a power interruption or system shutdown. To optimize the reconstruction of the superblock table or other similar operation data in the volatile memory, embodiments of the invention use a “snapshot entry” to identify the latest entry information, allowing the controller to quickly identify the most updated physical locations of the operation data portions and complete the reconstruction in an efficient manner.