Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: A light emitting device in an embodiment includes first and second light transmissive insulators and a light emitting diode arranged between them. First and second electrodes of the light emitting diode are electrically connected to a conductive circuit layer provided on a surface of at least one of the first and second light transmissive insulators. Between the first light transmissive insulator and the second light transmissive insulator, a third light transmissive insulator is embedded which has at least one of a Vicat softening temperature of 80° C. or higher and 160° C. or lower and a tensile storage elastic modulus of 0.01 GPa or more and 10 GPa or less.

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

Abstract: A microelectronic assembly is provided which includes a first element consisting essentially of at least one of semiconductor or inorganic dielectric material having a surface facing and attached to a major surface of a microelectronic element at which a plurality of conductive pads are exposed, the microelectronic element having active semiconductor devices therein. A first opening extends from an exposed surface of the first element towards the surface attached to the microelectronic element, and a second opening extends from the first opening to a first one of the conductive pads, wherein where the first and second openings meet, interior surfaces of the first and second openings extend at different angles relative to the major surface of the microelectronic element. A conductive element extends within the first and second openings and contacts the at least one conductive pad.

Abstract: An electronic device package including a substrate, a base film, a first seal, an electronic device and a second seal is provided. The first seal is disposed between the substrate and the base film and partially exposed by the base film. The electronic device is formed on the base film. The second seal disposed on the electronic device includes absorbents. A part of the second seal adheres to a part of the first seal exposed by the base film. The first seal and the second seal encapsulate the base film and the electronic device. The first seal and the second seal are the same host materials. A packaging method of an electronic device package is also provided.

Abstract: A multi-package unit having stacked packages is provided. A multi-package unit may include a first package and a second package mounted on the first package. The first package may be a leadframe package that includes metal leads extending beyond the perimeter of the first package. The first package may include a first integrated circuit die assembled within the first package using the wirebond configuration or the flip-chip configuration. The second package may be a leadframe package or a leadless package that includes a second integrated circuit die. The second package may be smaller than the first package. The first and second integrated circuit dies may be formed using different integrated circuit fabrication technologies.

Abstract: A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.

Abstract: A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate typically has a coefficient of thermal expansion matched to the coefficient of thermal expansion of a semiconductor device to be affixed to the substrate. The semiconductor device is typically attached to an exposed top surface of the substrate. The cavity package also includes a plastic portion molded to the leadframe forming a substrate cavity. The substrate cavity allows access to the exposed top surface of the substrate for affixing the semiconductor device. The cavity package also include a connective element for grounding a lid through an electrical path from the lid to the interposer.

Abstract: An organic light emitting display panel and associated methods, the panel including a substrate; an organic light emitting diode (OLED) on the substrate; and an encapsulation member to separate the OLED from an external environment, wherein the OLED includes a first electrode on the substrate; a pixel defining layer exposing the first electrode and including a flat planar surface and an inclined planar surface extending from the flat planar surface such that the inclined planar surface overlaps an edge of the first electrode; an organic layer, the organic layer including a first region on the first electrode and a second region on the inclined planar surface; and a second electrode on the organic layer, and wherein, in the second region, a thickness of the organic layer is decreased along a direction extending away from the first region.

Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically c

Abstract: An organic light-emitting diode display is disclosed. In one aspect, the display includes a substrate including a bending area and a non-bending area and a plurality of thin-film transistors (TFTs) formed in the non-bending area. The display also includes a plurality of first pixel electrodes and a plurality of second pixel electrodes formed over the TFTs and electrically connected to the TFTs, the first pixel electrodes formed in the bending area and the second pixel electrodes formed in the non-bending area.

Abstract: Disclosed is an organic light emitting device which facilitates to realize a long lifespan and to satisfy a color region, wherein the organic light emitting device may include an organic emitting layer including red, green and blue emitting layers, the organic emitting layer provided between first and second electrodes; and a plurality of dopants included in at least any one of the red, green and blue emitting layers, wherein a maximum intrinsic luminescence wavelength of any one dopant among the plurality of dopants is different from a maximum intrinsic luminescence wavelength of another dopant among the plurality of dopants.

Abstract: A semiconductor structure has a first layer that includes a first semiconductor material and a second layer that includes a second semiconductor material. The first semiconductor material is selectively etchable over the second semiconductor material using a first etching process. The first layer is disposed over the second layer. A recess is disposed at least in the first layer. Also described is a method of forming a semiconductor structure that includes a recess. The method includes etching a region in a first layer using a first etching process. The first layer includes a first semiconductor material. The first etching process stops at a second layer beneath the first layer. The second layer includes a second semiconductor material.

Abstract: Aspects for applying channel stress to Fin field-effect transistors (FETs) (FinFETs) using a self-aligned single diffusion break (SDB) isolation structure are disclosed. In one aspect, a FinFET-based circuit is provided. The FinFET-based circuit includes a semiconductor substrate and a Fin formed from the semiconductor substrate. The FinFET-based circuit also includes first and second FinFETs, each corresponding to the Fin. The FinFET-based circuit also includes a gate region disposed between the first FinFET and the second FinFET. An SDB isolation structure is formed in the Fin between the first FinFET and the second FinFET. The self-aligned SDB isolation structure is self-aligned with the gate region and electrically isolates the first FinFET and the second FinFET. The self-aligned SDB isolation structure applies stress to a first channel corresponding to the first FinFET and to a second channel corresponding to the second FinFET.

Abstract: A microelectronic package has a microelectronic element overlying or mounted to a first surface of a substrate and substantially rigid conductive posts projecting above the first surface or projecting above a second surface of the substrate remote therefrom. Conductive elements exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. An encapsulant overlies at least a portion of the microelectronic element and the surface of the substrate above which the conductive posts project, the encapsulant having a recess or a plurality of openings each permitting at least one electrical connection to be made to at least one conductive post. At least some conductive posts are electrically insulated from one another and adapted to simultaneously carry different electric potentials.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate structure over a substrate, forming a source/drain feature in the substrate adjacent the first gate structure, forming a dielectric layer over the first gate structure and the source/drain feature, removing a portion of the dielectric layer to form a first trench exposing the first gate structure and the source/drain feature, forming a first conductive feature in the first trench, removing a first portion of the first gate structure to form a second trench and forming a second conductive feature in the second trench.

Abstract: A semiconductor device includes a laminated substrate having circuit boards, an insulating plate, and a metal plate laminated, and warped convexly to the circuit board side; semiconductor chips fixed to the corresponding circuit boards; a base plate having a predetermined disposition region in which the laminated substrate is disposed, grooves disposed in the outer periphery of the disposition region, and projections disposed in positions in the disposition region adjacent to and inside the grooves. The grooves has on the projection side an inclination corresponding to an inclination caused by the warp of the laminated substrate. A joining material fills the space between the metal plate and the disposition region and covers the grooves and projections.

Abstract: A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.

Abstract: An organic light-emitting device includes: an anode; a wiring that is disposed side-by-side with and spaced from the anode; a light-emitting layer that is disposed above the anode, and includes an organic light-emitting material; an intermediate layer that is disposed above the light-emitting layer and the wiring; an organic functional layer that is disposed above the intermediate layer, and has an electron injection property or an electron transport property; a cathode that is disposed above the organic functional layer. The intermediate layer includes: a fluoride of a first metal, the first metal being an alkali metal or an alkaline-earth metal; and a second metal that has a property of cleaving a bond between the first metal and fluorine in the fluoride.

Abstract: A silicon germanium on insulator (SGOI) wafer having nFET and pFET regions is accessed, the SGOI wafer having a silicon germanium (SiGe) layer having a first germanium (Ge) concentration, and a first oxide layer over nFET and pFET and removing the first oxide layer over the pFET. Then, increasing the first Ge concentration in the SiGe layer in the pFET to a second Ge concentration and removing the first oxide layer over the nFET. Then, recessing the SiGe layer of the first Ge concentration in the nFET so that the SiGe layer is in plane with the SiGe layer in the pFET of the second Ge concentration. Then, growing a silicon (Si) layer over the SGOI in the nFET and a SiGe layer of a third concentration in the pFET, where the SiGe layer of a third concentration is in plane with the grown nFET Si layer.