Abstract: A superjunction bipolar transistor includes an active transistor cell area that includes active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body. A superjunction area overlaps the active transistor cell area and includes a low-resistive region and a reservoir region outside of the low-resistive region. The low-resistive region includes a first superjunction structure with a first vertical extension with respect to a first surface at the front side of the semiconductor body. The reservoir region includes no superjunction structure such that the reservoir region includes the semiconductor body that extends from a region located at the first surface to a drain region.

Abstract: A light-emitting diode (LED) package includes a light-emitting structure, an optical wavelength conversion layer on the light-emitting structure, and an optical filter layer on the optical wavelength conversion layer. The light-emitting structure includes a first-conductivity-type semiconductor layer, an active layer on the first-conductivity-type semiconductor layer, and a second-conductivity-type semiconductor layer on the active layer, and emits first light having a first peak wavelength. The optical wavelength conversion layer absorbs the first light emitted from the light-emitting structure and emits second light having a second peak wavelength different from the first peak wavelength. The optical filter layer reflects the first light emitted from the light-emitting structure and transmits the second light emitted from the optical wavelength conversion layer.

Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.

Abstract: Disclosed are an array substrate, a manufacturing method thereof, a sensor and a detection device. The array substrate includes: a base substrate; a thin-film transistor (TFT) being disposed on the base substrate and including a source electrode and an active layer; a passivation layer disposed on the TFT; a first metal layer disposed on the passivation layer; an insulating layer disposed on the first metal layer; a through hole structure running through the insulating layer, the first metal layer and the passivation layer; and a detection unit being disposed on the insulating layer and including a second metal layer, wherein the second metal layer makes direct contact with the source electrode via the through hole structure.

Abstract: The present invention relates to method for depositing an organic material for an organic light emitting device and an organic light emitting device manufactured thereby. The method includes the steps of: applying a premix in which a host and a dopant are premixed, to a first donor substrate; heating the premix by applying an electric field to the first donor substrate; depositing the host and the dopant separated into different layers on a second donor substrate, with the host or the dopant having a relatively low vaporization temperature first deposited from the premix onto the second donor substrate and then the dopant or the host having a relatively high vaporization temperature deposited later onto the second donor substrate; heating the host and the dopant by applying an electric field to the second donor substrate; and depositing the host and the dopant that are uniformly mixed on a target substrate.

Abstract: A III-N device includes a III-N layer structure including a III-N channel layer, a III-N barrier layer over the III-N channel layer, and a graded III-N layer over the III-N barrier layer having a first side adjacent to the III-N barrier layer and a second side opposite the first side; a first power electrode and a second power electrode; and a gate between the first and second power electrodes, the gate being over the III-N layer structure. A composition of the graded III-N layer is graded so the bandgap of the graded III-N layer adjacent to the first side is greater than the bandgap of the graded III-N layer adjacent to the second side. A region of the graded III-N layer is (i) between the gate and the second power electrode, and (ii) electrically connected to the first power electrode and electrically isolated from the second power electrode.

Abstract: The present application provides planar and stacked resistor structures that are embedded within an interconnect dielectric material in which the resistivity of an electrical conducting resistive material or electrical conducting resistive materials of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, a doped metallic insulator layer is formed atop a substrate. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer. The remaining doped metallic insulator layer and the electrical conducting resistive material layer are then patterned to provide the resistor structure.

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

Abstract: A device includes, among other things, a first vertical transistor device positioned above a semiconductor substrate. The first vertical transistor device includes a first gate structure, a first top spacer positioned above the first gate structure and having a first thickness in a vertical direction, and a first doped top source/drain structure positioned above the first top spacer. A second vertical transistor device positioned above the semiconductor substrate includes a second gate structure, a second top spacer positioned above the second gate structure and having a second thickness in a vertical direction less than the first thickness, and a second doped top source/drain structure positioned above the second top spacer.

Abstract: A resistor structure is provided that contains curved resistor elements. The resistor structure is embedded within an interconnect dielectric material and the resistivity of an electrical conducting resistive material of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, an electrical conducting metallic structure having a concave outermost surface is provided in a dielectric material layer. A doped metallic insulator layer is formed on the concave outermost surface of the metallic structure. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material. An interconnect dielectric material can then be formed to embed the entirety of the remaining doped metallic insulator layer and the electrical conducting resistive material.

Abstract: A resistor structure is provided that contains curved resistor elements. The resistor structure is embedded within an interconnect dielectric material and the resistivity of an electrical conducting resistive material of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, an electrical conducting metallic structure having a concave outermost surface is provided in a dielectric material layer. A doped metallic insulator layer is formed on the concave outermost surface of the metallic structure. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material. An interconnect dielectric material can then be formed to embed the entirety of the remaining doped metallic insulator layer and the electrical conducting resistive material.

Abstract: Disclosed is a method for the manufacture of a CEM device comprising forming a thin film of a correlated electron material having a predetermined electrical impedance when the CEM device in its relatively conductive (low impedance) state, wherein the forming of the CEM thin film comprises forming a d- or f-block metal or metal compound doped by a physical or chemical vapor deposition with a predetermined amount of a dopant comprising a back-donating ligand for the metal.

Abstract: A profile of a user may be constructed having at least one profile entry. A device having an integrated sensor assembly including at least one sensor may be associated with the user and operated according to a sensor configuration. Sensor data may be processed to extract a feature. Entry data may be determined for a profile entry based on the extracted feature so that the profile entry may incorporate the determined entry data. An exchangeable profile may be derived from the constructed profile, for example by using privacy data, and compensation from a third party may be received in return for the exchangeable profile.

Abstract: A quantum dot film and a display device are disclosed herein. The quantum dot film includes a substrate and at least one ultraviolet quantum dot disposed in the substrate and capable of emitting ultraviolet rays having a wavelength in a range of 190 to 280 nm.

Abstract: A mask includes a substrate, an effective pixel formation region and a reference pattern formation region. A pixel pattern for forming a pixel component that constitutes a pixel is arranged in the effective pixel formation region. A reference pattern for indicating a reference position where pixel pattern should be arranged in the effective pixel formation region is arranged in the reference pattern formation region. Pixel pattern is arranged to be displaced from the reference position toward a center side of the effective pixel formation region.

Abstract: A display substrate, a display apparatus and a production method of the display substrate are provided. The display substrate includes a plurality of pixel units arranged in an array. Each of the pixel units includes: a first electrode; a first connection portion connected with the first electrode; and a first connection line, the first connection portion being connected to the first connection line through a first via hole. The first connection line of at least one of the pixel units is connected with the first connection line of the pixel unit positioned on an upper side of the at least one of the pixel units and the first connection line of the pixel unit positioned on a lower side of the at least one of the pixel units.

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

Abstract: Provided are perovskite nanocrystalline particle and an optoelectronic device using the same. The perovskite nanocrystalline particle may include a perovskite nanocrystalline structure while being dispersible in an organic solvent. Accordingly, the perovskite nanocrystalline particle in accordance with the present invention has therein a perovskite nanocrystal having a crystalline structure in which FCC and BCC are combined; can form a lamellar structure in which an organic (or A site) plane and an inorganic plane are alternately stacked; and can show high color purity since excitons are confined to the inorganic plane.

Abstract: Provided is a III-nitride semiconductor light-emitting device having excellent device lifetime as compared with conventional devices and a method of producing the same. A III-nitride semiconductor light-emitting device 100 has an n-type semiconductor layer 30, a light emitting layer 40 containing at least Al, an electron blocking layer 50, and a p-type semiconductor layer 60 in this order. The light emitting layer 40 has a quantum well structure having well layers 41 and barrier layers 42. The electron blocking layer 50 is adjacent to the light emitting layer 40 and is formed from a layer having an Al content higher than that of the barrier layers 42 and the p-type semiconductor layer 60. The electron blocking layer 50 has a Si-based doped region layer 50a.

Abstract: A semiconductor structure includes a substrate having a frontside surface and a backside surface. A through-substrate via extends into the substrate from the frontside surface. The through-substrate via comprises a top surface. A metal cap covers the top surface of the through-substrate via. A plurality of cylindrical dielectric plugs is embedded in the metal cap. The cylindrical dielectric plugs are distributed only within a central area of the metal cap. The central area is not greater than a surface area of the top surface of the through-substrate via.