Abstract: A direct-deposition system capable of forming a high-resolution pattern of material on a substrate is disclosed. Vaporized atoms from an evaporation source pass through an aperture pattern of a shadow mask to deposit on the substrate in the desired pattern. Prior to reaching the shadow mask, the vaporized atoms pass through a collimator that operates as a spatial filter that blocks any atoms not travelling along directions that are nearly normal to the substrate surface. As a result, the vaporized atoms that pass through the shadow mask exhibit little or no lateral spread (i.e., feathering) after passing through its apertures and the material deposits on the substrate in a pattern that has very high fidelity with the aperture pattern of the shadow mask. The present invention, therefore, mitigates the need for relatively large space between regions of deposited material normally required in the prior art, thereby enabling high-resolution patterning.

Abstract: Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

Abstract: A method of fabricating an integrated fan-out package is provided. The method includes the followings. An integrated circuit component is mounted on a carrier. An insulating encapsulation is formed on the carrier to encapsulate sidewalls of the integrated circuit component. A plurality of conductive pillars are formed on the integrated circuit component and a dielectric layer is formed to cover the integrated circuit component and the insulating encapsulation, wherein the plurality of conductive pillars penetrate through the dielectric layer and are electrically connected to the integrated circuit component. A redistribution circuit structure is formed on the dielectric layer and the plurality of conductive pillars, wherein the redistribution circuit structure is electrically connected to the integrated circuit component through the plurality of conductive pillars, and the redistribution circuit structure and the insulating encapsulation are spaced apart by the dielectric layer.

Abstract: The present disclosure relates to a solid-state imaging device capable of receiving light entering a gap between pixel regions of imaging units by the pixel region when a plurality of imaging units is arranged, a method of manufacturing the same, and an electronic device. A CMOS image sensor includes a pixel region formed of a plurality of pixels. A convex lens is provided for each of a plurality of CMOS image sensors. A plurality of CMOS image sensors is arranged on a supporting substrate. The present disclosure is applicable to a solid-state imaging device and the like in which a plurality of CMOS image sensors is arranged on the supporting substrate, for example.

Abstract: There is provided a filler-filled film, a sheet film, a stacked film, a bonded body, and a method for producing a filler-filled film, the filler-filled film including: a film main body; a plurality of concavities formed on a surface of the film main body; and a filler put in each of the concavities. A diameter of an opening surface of the concavity is at least larger than a visible light wavelength, an arrangement pattern of the concavities has periodicity along a length direction of the film main body, and the difference between the rate of filling of the fillers in one end portion of the film main body and the rate of filling of the fillers in another portion of the film main body is less than 0.5%.

Abstract: A GaN-based power electronic device and a method for manufacturing the same is provided. The GaN-based power electronic device comprising a substrate and an epitaxial layer over the substrate. The epitaxial layer comprises a GaN-based heterostructure layer, a superlattice structure layer and a P-type cap layer. The superlattice structure layer is provided over the heterostructure layer, and the P-type cap layer is provided over the superlattice structure layer. By using this electronic device, gate voltage swing and safe gate voltage range of the GaN-based power electronic device manufactured on the basis of the P-type cap layer technique may be further extended, and dynamic characteristics of the device may be improved. Therefore, application process for the GaN-based power electronic device that is based on the P-type cap layer technique will be promoted.

Abstract: In accordance with the following step of a method of manufacturing a MOSFET, a first cutting step of cutting a silicon carbide wafer along a plane substantially parallel to a {11-20} plane is performed. After the first cutting step, a second cutting step of cutting the silicon carbide wafer along a plane substantially perpendicular to the {11-20} plane and substantially perpendicular to the first main surface is performed.

Abstract: A semiconductor arrangement comprising; a die of III-V semiconductor material; a resistor element integrated in the die, the resistor element comprising a track defined by a first implant material in the III-V semiconductor material of the die, said track electrically isolated from substantially the remainder of the die by an isolation region that surrounds the track.

Abstract: Provided is a resistance random access memory device comprising: a first electrode; a second electrode; and a metallic oxide formed between the first electrode and the second electrode. Particularly, provided is a resistance random access memory device wherein the metallic oxide comprises a first crystal grain and a second crystal grain which differ from each other in crystallographic orientation and form a boundary area; wherein a surface is intervened between the first crystal grain and the second crystal grain in the boundary area, the surface having a surface index corresponding to a surface crystallographically consisting only of oxygen among the crystal faces of the metallic oxide; and wherein the boundary area is a surface in which an electrically conductive path is formed when voltage is applied between the first electrode and the second electrode.

Abstract: A compound semiconductor device includes a first protection film which covers a surface of a compound semiconductor layer, where the first protection film is an insulating film whose major constituent is Si and at least one element between N and O, and a hydrophobic layer containing Si—CxHy is formed at a surface thereof.

Abstract: A liquid-crystal display device, including: a first data line and a second data line each lengthwise extended in a first direction and spaced apart from each other, a gate line lengthwise extended in a second direction different from the first direction, the gate line defining: a first region thereof overlapping the first data line, a second region thereof overlapping the second data line and a third region thereof extended between the first region and the second region, and a pixel including a switching element, a first electrode of the switching element being connected to the first data line and a second electrode of the switching element overlapping each of the first to third regions. In the first direction, a width of the third region is smaller than a width of each of the first and second regions.

Abstract: According to the present disclosure, optoelectronic semiconductor chip includes at least one n-doped semiconductor layer, at least one p-doped semiconductor layer and one active layer arranged between the at least one n-doped semiconductor layer and the at least one p-doped semiconductor layer. The p-doped semiconductor layer is electrically contacted by means of a first metallic connection layer, and a reflection-enhancing dielectric layer sequence is arranged between the p-doped semiconductor layer and the first connection layer, which dielectric layer sequence includes a plurality of dielectric layers with different refractive indices.

Abstract: A wireless transmission system disclosed herein includes a radiating structure integrated into a computing device case that substantially encloses electronics of a computing device. The radiating structure includes an insulator that forms a boundary with the metal plate on the computing device case. A proximity sensor collects data from an exposure point located within the radiating structure.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a plural fin structures, two gates, a protection layer and an interlayer dielectric layer. The fin structures are disposed on a substrate. The two gates are disposed on the substrate across the fin structures. The protection layer is disposed on the substrate, surrounded sidewalls of the two gates. The interlayer dielectric layer is disposed on the substrate, covering the fin structures and the two gates.

Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.

Abstract: A light emitting element includes an n-type semiconductor layer having an upper surface; a p-type semiconductor layer over a portion of the upper surface of the n-type semiconductor layer, the p-type semiconductor layer having an upper surface; a protective film continuously covering the n-type semiconductor layer and the p-type semiconductor layer, the protective film defining an n-side opening at the upper surface of the n-type semiconductor layer and a p-side opening at an upper surface of the p-type semiconductor layer; a p-side electrode on the upper surface of the p-type semiconductor layer that is exposed in the p-side opening; an n-side electrode on the upper surface of the n-type semiconductor layer that is exposed at the n-side opening, n-side electrode having an n-side light-transmissive electrode; and an n-side pad electrode on the upper surface of the n-side light-transmissive electrode.

Abstract: A semiconductor device of a double-side cooling structure having a bus bar electrically connected, and coolers independently arranged on both sides of the semiconductor device for cooling is provided. The semiconductor device includes: a semiconductor chip including an element, and has a first main surface and a second main surface; a sealing resin body having a first surface and a second surface and also having a side surface; a first heatsink arranged facing the first main surface and electrically connected to the first main electrode; and a second heatsink arranged facing the second main surface and electrically connected to the second main electrode. The first heatsink is exposed only to the first surface. The second heatsink is exposed only to the second surface. An exposed surface of a heatsink to be electrically connected to the bus bar has a heat dissipation region, and an electrical connection region.

Abstract: Provided is a SiC substrate treatment method for, with respect to a SiC substrate (40) that has, on its surface, grooves (41), activating ions while preventing roughening of the surface of the substrate. In the method, an ion activation treatment in which the SiC substrate (40) is heated under Si vapor pressure is performed to the SiC substrate (40) has, on its surface, an ion implantation region (46) in which ions have been implanted, and has the grooves (41) provided in a region including at least the ion implantation region (46), thereby ions that are implanted in the SiC substrate (40) is activated while etching the surface of the substrate.

Abstract: To provide a method for producing a Group III element nitride crystal by growing it on a plane on the ?c-plane side as a crystal growth plane. The present invention is a method for producing a Group III element nitride crystal, including a vapor phase growth step of growing a Group III element nitride crystal 12 on a crystal growth plane of a Group III element nitride seed crystal 11 by vapor deposition. The vapor phase growth step is a step of causing a Group III metal, an oxidant, and a nitrogen-containing gas to react with one another to grow the Group III element nitride crystal 12 or includes: a reduced product gas generation step of causing a Group III element oxide and a reducing gas to react with each other to generate a gas of a reduced product of the Group III element oxide; and a crystal generation step of causing the gas of the reduced product and a nitrogen-containing gas to react with each other to generate the Group III element nitride crystal 12.

Abstract: Vertical meander inductors for small core voltage regulators and approaches to fabricating vertical meander inductors for small core voltage regulators are described. For example, a semiconductor die includes a substrate. An integrated circuit is disposed on an active surface of the substrate. An inductor is coupled to the integrated circuit. The inductor is disposed conformal with an insulating layer disposed on an essentially planar surface of the substrate. The insulating layer has an undulating topography.