Abstract: The device manufacturing method includes a length measuring step (S5) of, on the basis of an observation target image of an SEM image taken from a direction having a predetermined angle from a direction perpendicular to a plane of a substrate, measuring the thickness of a target object, or the depth of etching, formed on the substrate. In addition, in the length measuring step, an etching angle made by a cross section of the etching and the direction perpendicular to the plane of the substrate is calculated from processing data of the target object, and the thickness of the target object or the depth of the etching is measured on the basis of the calculated etching angle.

Abstract: Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.

Abstract: A laser distance measuring device and a control method for the same are disclosed. More specifically, disclosed herein are a laser distance measuring device capable of quickly measuring horizontal and vertical distances using laser and a control method for the same. The laser distance measuring device may include a light transmitter, a light receiver, a sensing unit, and a controller configured to perform an control operation to emit split laser through the light transmitter, acquire time difference information indicating a difference between a time to emit the split laser and a time to sense, through the sensing unit, the split laser reflected from a target position, and calculate a distance to the target position using the time difference information.

Abstract: A device includes a surface profile optical element, including a substrate and a plurality of bi-layer stacks on the substrate. Each bi-layer stack of the plurality of bi-layer stacks includes a plurality of bi-layers. Each bi-layer of the plurality of bi-layers includes an etch-stop layer and a bulk layer. The etch stop layer includes an etch stop layer index of refraction. The bulk layer includes a bulk layer index of refraction. A ratio of the etch stop layer index of retraction and the bulk layer index of refraction is between 0.75 and 1.25.

Abstract: The present invention provides a printed circuit board fabricated by a Non-Plating Process that includes at least one plating bar disposed around at least one package unit of the printed circuit board. The package unit includes at least one ground line, at least one power line and a plurality of signal lines. The ground line has a first contact pad exposed on a surface of the printed circuit board, and at least one of the ground lines is connected to the plating bar. The power line has a second contact pad exposed on the surface, and at least one of the power lines is connected to the neighboring plating bar. The signal line has a third contact pad exposed on the surface.

Abstract: The present technology relates to techniques of preventing intrusion of moisture into a chip. Various illustrative embodiments include image sensors that include: a substrate; a plurality of layers stacked on the substrate; the plurality of layers including a photodiode layer having a plurality of photodiodes formed on a surface of the photodiode layer; the plurality of layers including at least one layer having a groove formed such that a portion of the at least one layer is excavated; and a transparent resin layer formed above the photodiode layer and formed in the groove. The present technology can be applied to, for example, an image sensor.

Abstract: The present application provides planar and stacked resistor structures that are embedded within an interconnect dielectric material in which the resistivity of an electrical conducting resistive material or electrical conducting resistive materials of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, a doped metallic insulator layer is formed atop a substrate. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer. The remaining doped metallic insulator layer and the electrical conducting resistive material layer are then patterned to provide the resistor structure.

Abstract: A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

Abstract: A method of forming a silicon film, a germanium film or a silicon germanium film on a target substrate having a fine recess formed on a surface of the target substrate by a chemical vapor deposition method includes placing the target substrate having the fine recess in a processing container, and supplying a film forming gas containing an element constituting a film to be formed and a chlorine-containing compound gas into the processing container. Adsorption of the film forming gas at an upper portion of the fine recess is selectively inhibited by the chlorine-containing compound gas.

Abstract: Various nanostructures, including silicon nanowires and encapsulated silicon nanoislands, and methods of making the nanostructures are provided. The methods can include providing a fin structure extending above a substrate, wherein the fin structure has at least one silicon layer and at least two silicon:germanium alloy (SiGe) layers that define sidewalls of the fin structure; and annealing the fin structure in oxygen to form a silicon nanowire assembly. The silicon nanowire assembly can include a silicon nanowire, a SiGe matrix surrounding the silicon nanowire; and a silicon oxide layer disposed on the SiGe matrix. The annealing can be, for example, at a temperature between 800° C. and 1000° C. for five minutes to sixty minutes. The silicon nanowire can have a long axis extending along the fin axis, with perpendicular first and second dimensions extending less than 50 nm along directions perpendicular to the fin axis.

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

Abstract: Provided are a graphene-based laminate and a method of preparing the graphene-based laminate. The graphene-based laminate may include a substrate; a graphene layer formed on at least one surface of the substrate; and an inorganic layer formed on the graphene layer and including a fluorine-containing lithium compound.

Abstract: A resistor structure is provided that contains curved resistor elements. The resistor structure is embedded within an interconnect dielectric material and the resistivity of an electrical conducting resistive material of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, an electrical conducting metallic structure having a concave outermost surface is provided in a dielectric material layer. A doped metallic insulator layer is formed on the concave outermost surface of the metallic structure. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material. An interconnect dielectric material can then be formed to embed the entirety of the remaining doped metallic insulator layer and the electrical conducting resistive material.

Abstract: In accordance with various embodiments, the disclosed subject matter provides a display device and a related fabricating method. In some embodiments, the display device comprises: a substrate and a plurality of display units on the substrate, wherein each of the plurality of display units comprises: a first color sub-pixel, comprising a first quantum dot material and a first light source, wherein the first color sub-pixel is configured to provide a first color light by stimulating the first quantum dot material with the first light source; and a second color sub-pixel, comprising a second quantum dot material and a second light source, wherein the second color sub-pixel is configured to provide a second color light by stimulating the second quantum dot material with the second light source.

Abstract: A method of manufacturing a switching element includes forming a first electrode layer over a substrate, forming a switching structure on the first electrode layer, and forming a second electrode layer on the switching structure. The switching structure includes a plurality of unit switching layers that includes a first unit switching layer and a second unit switching layer. Forming the first unit switching layer includes forming a first unit insulation layer, and injecting first dopants into the first unit insulation layer by performing a first ion implantation process. Forming the second unit switching layer includes forming a second unit insulation layer, and injecting second dopants into the second unit insulation layer by performing a second implantation process.

Abstract: A method of fabricating an embedded nonvolatile memory device is disclosed. A semiconductor substrate having thereon a fin body protruding from an isolation layer is provided. A charge storage layer crossing the fin body is formed. An inter-layer dielectric layer is deposited on the semiconductor substrate. The inter-layer dielectric layer is polished to expose a top surface of the charge storage layer. The charge storage layer is then recess etched and cut into separate charge storage structures. A high-k dielectric layer is formed on the charge storage structures. A word line is formed on the high-k dielectric layer.

Abstract: After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed on sidewalls of a lower portion of the gate stack that contacts the plurality of semiconductor fins and a gate spacer having a width greater than a width of the gate liner is formed on sidewalls of an upper portion of the gate stack that is located above the plurality of semiconductor fins. The width of the gate spacer thus is not limited by the fin pitch, and can be optimized to improve the device performance.

Abstract: A semiconductor device includes a pixel portion having a first thin film transistor and a driver circuit having a second thin film transistor. Each of the first thin film transistor and the second thin film transistor includes a gate electrode layer, a gate insulating layer, a semiconductor layer, a source electrode layer, and a drain electrode layer. Each of the layers of the first thin film transistor has a light-transmitting property. Materials of the gate electrode layer, the source electrode layer and the drain electrode layer of the first thin film transistor are different from those of the second transistor, and each of the resistances of the second thin film transistor is lower than that of the first thin film transistor.

Abstract: The present invention relates to a thin film transistor array substrate and a method of manufacturing the same.

Abstract: A quantum dot light-emitting device includes: a first electrode; a second electrode opposite to the first electrode; an emission layer between the first electrode and the second electrode, the emission layer including quantum dots; and an inorganic layer between the emission layer and the second electrode, the inorganic layer including a metal halide.