Abstract: A light-emitting device includes a substrate, a semiconductor stack formed on the substrate, a conductive structure, first and second contact electrodes, an insulating stack, and first and second electrode pads. The second electrode pad is disposed in an opening of the insulating stack and connected to the second contact electrode. An upper surface of the second electrode pad includes a platform area and a depression area, wherein a ratio of a projected area A1 of the platform area to to a sum A2 of projected areas of the platform area and the depression area ranges ranges from 50%-80%.

Abstract: A solid-state imaging element according to the present technology includes a pixel array unit in which a plurality of pixels each having a photoelectric conversion portion is arranged, the pixel array unit includes, as the pixels, a first pixel for obtaining a gradation signal indicating an intensity of received light and a second pixel for detecting that a change in an amount of received light exceeds a predetermined threshold value, and a volume of a photoelectric conversion portion included in the second pixel is larger than a volume of a photoelectric conversion portion included in the first pixel.

Abstract: A growth method of LED epitaxy comprises: providing a layer of substrate, wherein the substrate is an Al2O3 substrate or an Al2O3/SiO2 composite substrate; successively depositing and growing a SiC buffer layer and a u-GaN layer on the substrate; wherein the temperature used for depositing the SiC buffer layer is 650~1550 degrees; the gas used for depositing the SiC buffer layer is a silicon source gas and a carbon source gas, a flow rate of the silicon source gas is 1~1000 sccm, and a flow rate of the carbon source gas is 1~1000 sccm; a gas carrier gas used for depositing the SiC buffer layer has a flow rate of 10~500 slm; the SiC buffer layer is deposited at a pressure of 100~700 torr; the SiC buffer layer is deposited for a thickness of 10~1000 A.

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor package on the first redistribution structure, the first semiconductor package including a first semiconductor chip which includes a first device layer and a first semiconductor substrate including a through electrode, a second semiconductor chip which is on the first semiconductor chip and includes a second device layer and a second semiconductor substrate, and a molding member surrounding the first semiconductor chip, a second redistribution structure on an upper surface of the molding member, and a second semiconductor package on the second redistribution structure, the second semiconductor package including a third semiconductor chip, wherein the second semiconductor chip is apart from the second semiconductor package in a horizontal direction, and an upper surface of the second semiconductor chip is higher than the upper surface of the molding member.

Abstract: A method of making a memory device includes forming an alternating stack of insulating layers and sacrificial material layers, where a silicon oxycarbide liner is interposed between a first sacrificial material layer and a first insulating layer, and the first sacrificial material layer is direct contact with a second insulating layer or a dielectric material layer composed of a silicon oxide material, forming a memory opening through the alternating stack, forming a memory opening fill structure in the memory opening, forming backside recesses by removing the sacrificial material layers selective to the silicon oxycarbide liner, and forming electrically conductive layers in the backside recesses.

Abstract: The present invention provides a MEMS pressure sensor and a manufacturing method. The pressure is formed by a top cap wafer, a MEMS wafer and a bottom cap wafer. The MEMS wafer comprises a frame and a membrane, the frame defining a cavity. The membrane is suspended by the frame over the cavity. The bottom cap wafer closes the cavity. The top cap wafer has a recess defining with the membrane a capacitance gap. The top cap wafer comprises a top cap electrode located over the membrane and forming, together with the membrane, a capacitor to detect a deflection of the membrane. Electrical contacts on the top cap wafer are connected to the top cap electrode. A vent extends from outside of the sensor into the cavity or the capacitance gap. The pressure sensor can include two cavities and two capacitance gaps to form a differential pressure sensor.

Abstract: A solution for fabricating a semiconductor structure and the corresponding semiconductor structure are provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.

Abstract: A power device comprising a substrate, a first wide bandgap semiconductor material positioned over the substrate, wherein the substrate comprises a second wide bandgap semiconductor material different from the first bandgap semiconductor material, a high voltage transistor formed in the first wide bandgap semiconductor material, and a high voltage diode associated with the substrate, wherein at least part of the high voltage diode is positioned below at least part of the high voltage transistor. The high voltage diode comprises a drift region, the drift region formed in the second-wide bandgap material.

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

Abstract: An image sensor includes a substrate having a plurality of first pixel regions configured to generate image information and a plurality of second pixel regions configured to detect phase information, a grid pattern on the substrate and dividing a plurality of spaces corresponding to each of the plurality of first pixel regions and the plurality of second pixel regions. The image sensor also includes a plurality of color filters respectively in first spaces of the plurality of spaces, excluding second spaces corresponding to the plurality of second pixel regions, a plurality of polarization patterns respectively in the second spaces and partitioning the second spaces, and a microlens layer including a plurality of first microlenses respectively on the plurality of color filters.

Abstract: An epitaxial structure including a first epitaxial layer, a second epitaxial layer, and an interface treatment layer is provided. The first epitaxial layer is an ohmic contact layer. The second epitaxial layer is disposed on the first epitaxial layer and is a phosphide compound layer, where a material of the second epitaxial layer is different from a material of the first epitaxial layer. The interface treatment layer contacts the first epitaxial layer and the second epitaxial layer and is located between the first epitaxial layer and the second epitaxial layer. An image contrast ratio of a transmission electron microscope (TEM) of the interface treatment layer to the first epitaxial layer and an image contrast ratio of the TEM of the interface treatment layer to the second epitaxial layer are both greater than 1.005. A method for forming an epitaxial structure is also provided.

Abstract: A III-nitride LED with simultaneous visible and ultraviolet (UV) emission, in which the visible emission is due to conventional InGaN active region mechanisms and the UV emission occurs due to Auger carrier injection into a UV light emitting region, such as impurity-doped AlGaN. The primary application for the III-nitride LED is general airborne pathogen inactivation to prevent the transmission of airborne-mediated pathogens while being safe for humans.

Abstract: A display device includes an active layer, a gate electrode on the active layer, a conductive layer on the gate electrode and connected to the active layer, a pixel electrode which is on the conductive layer and connected to the conductive layer, and a connection electrode which connects the conductive layer connected to the active layer, to the pixel electrode. The connection electrode which connects the conductive layer connected to the active layer, to the pixel electrode, has a tensile strength less than or equal to a tensile strength of the active layer.

Abstract: A method for manufacturing a display device is provided. The method includes: placing a light emitting element on a substrate including cell areas; placing an insulating layer on the light emitting element; and separating the cell areas from each other. Light emitting panels are located on the substrate, correspond to each of the cell areas, and include the light emitting element. The separating of the cell areas from each other includes electrically separating the light emitting panels from each other. The electrically separating the light emitting panels from each other is performed after the placing of the insulating layer.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: An image sensor includes a first unit. The first unit includes a first photodiode having a first dimension, a second photodiode disposed adjacent the first photodiode and having a second dimension that is greater than the first dimension, a first color filter overlapping the first photodiode and the second photodiode, and a first internal reflector disposed in the first color filter and overlapping the first photodiode. The first internal reflector has an inclined light receiving surface inclined from a top surface of the first color filter toward the second photodiode, and a refraction index of the first internal reflector is smaller than a refraction index of the first color filter.

Abstract: A semiconductor package includes a base film having a first mount section, a first folding section, a second folding section, and a second mount section. A first semiconductor chip is disposed on the first mount section of the base film. A second semiconductor chip is disposed on the second mount section of the base film. Test pads are disposed on the first or second folding sections of the base film and is connected to each of the first and second semiconductor chips. Connection pads are disposed on the first or second mount sections of the base film and are connected to each of the first and second semiconductor chips. The first and second folding sections vertically overlap each other. The test pads are interposed between and buried by the first and second folding sections.

Abstract: An imaging element, includes a pixel array in which a plurality of pixels including photoelectric conversion elements are arranged in a two-dimensional array, and an optical element array in which optical elements composed of a plurality of columnar structure bodies arranged opposite to a pixel array and guiding incident light to a corresponding photoelectric conversion element are arranged in a two-dimensional array, wherein the plurality of columnar structure bodies are formed in a width having a phase characteristic for guiding light to a photoelectric conversion element directly below a columnar structure body in accordance with an incident angle of the incident light of each columnar structure body when viewed in a plan view and are formed at a same height when viewed in a side view.

Abstract: An image sensor includes a color unit pixel comprising sub-pixels arranged in an m×n matrix on a substrate, and a pixel isolation structure isolating the sub-pixels from each other in the color unit pixel. The pixel isolation structure includes an outer isolation film surrounding the color unit pixel, at least one inner isolation film including a portion between two sub-pixels, which are adjacent to each other, among the sub-pixels, a doped isolation liner covering opposite sidewalls of the at least one inner isolation film, and at least one doped isolation pillar contacting at least two sub-pixels selected from the sub-pixels. The at least one doped isolation pillar and the at least one inner isolation film are arranged to define a size of a partial region of each of the sub-pixels.