Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings extending through the alternating stack, and memory opening fill structures located in the memory openings and containing a respective vertical semiconductor channel and a respective memory film. Each of the electrically conductive layers includes a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures, an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers, and a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers. The memory opening fill structures are formed after performing a halogen outgassing anneal through the memory openings to reduce or eliminate the halogen outgassing damage in the layers of the memory film.

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure, which has an upper fin structure made of SiGe and a bottom fin structure made of a different material than the upper fin structure, is formed, a cover layer is formed over the fin structure, a thermal operation is performed on the fin structure covered by the cover layer, and a source/drain epitaxial layer is formed in a source/drain region of the upper fin structure. The thermal operation changes a germanium distribution in the upper fin structure.

Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.

Abstract: A device includes: (1) a boron arsenide substrate; and (2) an integrated circuit disposed in or over the boron arsenide substrate.

Abstract: An arrangement is disclosed. The arrangement comprises at least one semiconductor structure configured to convert a primary radiation into a secondary radiation; an encapsulation layer covering the at least one semiconductor structure; and at least one reflective layer arranged on the encapsulation layer. The semiconductor structure is arranged in a center of the arrangement, and a lateral extent of the arrangement is chosen such that an optically resonant condition is fulfilled for a wavelength of the secondary radiation in the encapsulation layer. Methods for producing an arrangement and an optoelectronic device are also disclosed.

Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a plurality of first transistors each including a single crystal channel; a first metal layer disposed over the plurality of first transistors; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; a via disposed through the second level, where at least one of the plurality of second transistors includes a metal gate, where an average thickness of the fifth metal layer is greater than an average thickness of the third metal layer by at least 50%; and at least one Electrostatic discharge (“ESD”) structure.

Abstract: Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof are disclosed herein. An exemplary metal gate includes a first portion, a second portion, and a third portion. The second portion is disposed between the first portion and the third portion. The first portion includes a first gate dielectric layer, a first p-type work function layer, and a first n-type work function layer. The second portion includes a second gate dielectric layer and a second p-type work function layer. The third portion includes a third gate dielectric layer, a third p-type work function, and a second n-type work function layer. The second p-type work function layer separates the first n-type work function layer from the second n-type work function layer, such that the first n-type work function layer does not share an interface with the second n-type work function layer.

Abstract: A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

Abstract: An ESD protection device protects a circuit from TLPs between a first terminal and a second terminal. The device includes an NPN discharge structure and a PNP triggering device. The first terminal is coupled to the p-doped emitter and the n-doped base of the PNP triggering device and also the n-doped emitter of the NPN discharge structure. The second terminal is coupled to the n-doped collector of the NPN discharge structure. The p-doped collector of the PNP triggering device is coupled to the p-doped base of the NPN discharge structure. A TLP causes base-collector junction breakdown in the PNP triggering device, which results in a current through the PNP triggering device. That current is injected into the base of the NPN discharge structure, which results in a larger discharge current through the NPN discharge structure. The device provides high holding voltage ESD protection device with snapback.

Abstract: Provided are interconnects for interconnecting a set of battery cells, assemblies comprising these interconnects, methods of forming such interconnects, and methods of forming such assemblies. An interconnect includes a conductor comprising two portions electrically isolated from each other. At least one portion may include two contacts for connecting to battery cells and a fuse forming an electrical connection between these two contacts. The interconnect may also include an insulator adhered to the conductor and mechanically supporting the two portions of the conductor. The insulator may include an opening such that the fuse overlaps with this opening, and the opening does not interfere with the operation of the fuse. In some embodiments, the fuse may not directly interface with any other structures. Furthermore, the interconnect may include a temporary substrate adhered to the insulator such that the insulator is disposed between the temporary substrate and the conductor.

Abstract: Embodiments of the invention are directed to a semiconductor device structure that includes a first channel region over a substrate, a second channel region over the first channel region, and a merged source or drain (S/D) region over the substrate and adjacent to the first channel region and the second channel region. The merged S/D region is communicatively coupled to the first channel region and the second channel region. A wrap-around S/D contact is configured such that it is on a top surface, sidewalls, and a bottom surface of the merged S/D region.

Abstract: Photolithography overlay errors are a source of patterning defects, which contribute to low wafer yield. An interconnect formation process that employs a patterning photolithography/etch process with self-aligned interconnects is disclosed herein. The interconnection formation process, among other things, improves a photolithography overlay (OVL) margin since alignment is accomplished on a wider pattern. In addition, the patterning photolithography/etch process supports multi-metal gap fill and low-k dielectric formation with voids.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.

Abstract: Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

Abstract: A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.

Abstract: A semiconductor device with high productivity is provided. The semiconductor device includes a first and a second transistor and a first and a second capacitor. The first and the second transistor include gate electrodes and back gate electrodes. The second transistor is provided in a layer above the first transistor, and the second capacitor is provided in a layer above the first capacitor. One electrode of the first capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor and electrically connected to one of a source electrode and a drain electrode of the second transistor. The other electrode of the first capacitor is formed in the same layer as the back gate electrode of the second transistor.

Abstract: An image sensor including a plurality of avalanche photodiodes formed inside and on top of a semiconductor substrate of a first conductivity type having a front side and a back side, wherein: trenches vertically extend in the substrate from its front side to its back side, the trenches having, in top view, the shape of a continuous grid laterally delimiting a plurality of substrate islands, each island defining a pixel including a single individually-controllable avalanche photodiode, and including a doped area of collection of an avalanche signal of the pixel photodiode the lateral walls of the trenches are coated with a first semiconductor layer having a conductivity type opposite to that of the collection area, and a conductive region extends in the trenches, the conductive region being in contact with the surface of the first semiconductor layer opposite to the substrate.

Abstract: The present disclosure relates to an array substrate and a method for manufacturing the same. The array substrate includes a substrate, a thin film transistor located on the substrate, a light emitting device located on the substrate and spaced apart from the thin film transistor in a direction parallel to a surface of the substrate, and a light shielding portion located between the thin film transistor and the light emitting device for shielding a light from the light emitting device. The light shielding portion surrounds the light emitting layer.