Patents Examined by Nilufa Rahim
  • Patent number: 11152214
    Abstract: A method of forming a semiconductor device that includes forming a metal oxide material on a III-V semiconductor channel region or a germanium containing channel region; and treating the metal oxide material with an oxidation process. The method may further include depositing of a hafnium containing oxide on the metal oxide material after the oxidation process, and forming a gate conductor atop the hafnium containing oxide. The source and drain regions are on present on opposing sides of the gate structure including the metal oxide material, the hafnium containing oxide and the gate conductor.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, John Bruley, Eduard A. Cartier, Martin M. Frank, Vijay Narayanan, John Rozen
  • Patent number: 11152533
    Abstract: Techniques are disclosed for utilizing an etchant-accessible carrier substrate that enables etching through the carrier substrate. More particularly, an etchant is provided access to the adhesive layer via the etchant-accessible carrier substrate via one or more holes in the etchant-accessible carrier substrate. The size and/or pattern of the holes may vary, depending on desired functionality. The etching process may be optionally stopped prior to the removal of all of the adhesive layer such that at least a portion of the adhesive layer remains, which can help ensure the light-emitting structures do not slip off of the etchant-accessible carrier substrate as the etchant-accessible carrier substrate is moved from one location to another during the fabrication process.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 19, 2021
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Daniel Bryce Thompson, Daniel Brodoceanu, Pooya Saketi
  • Patent number: 11145548
    Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 12, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidefumi Saeki, Atsushi Harikai, Shogo Okita
  • Patent number: 11145657
    Abstract: A 3D semiconductor device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer which includes second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provide first connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the third layer includes crystalline silicon, and where the second level includes at least one scan-chain to support circuit test.
    Type: Grant
    Filed: July 4, 2021
    Date of Patent: October 12, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11145748
    Abstract: One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Carlos H. Diaz
  • Patent number: 11133401
    Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju
  • Patent number: 11130670
    Abstract: A device includes a substrate, a routing conductive line over the substrate, a dielectric layer over the routing conductive line, and an etch stop layer over the dielectric layer. A Micro-Electro-Mechanical System (MEMS) device has a portion over the etch stop layer. A contact plug penetrates through the etch stop layer and the dielectric layer. The contact plug connects the portion of the MEMS device to the routing conductive line. An escort ring is disposed over the etch stop layer and under the MEMS device, wherein the escort ring encircles the contact plug.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Ying Tsai, Hung-Hua Lin, Hsin-Ting Huang, Lung Yuan Pan, Jung-Huei Peng, Yao-Te Huang
  • Patent number: 11127601
    Abstract: A method of processing and passivating an implanted workpiece is disclosed, wherein, after passivation, the fugitive emissions of the workpiece are reduced to acceptably low levels. This may be especially beneficial when phosphorus, arsine, germane or another toxic species is the dopant being implanted into the workpiece. In one embodiment, a sputtering process is performed after the implantation process. This sputtering process is used to sputter the dopant at the surface of the workpiece, effectively lowering the dopant concentration at the top surface of the workpiece. In another embodiment, a chemical etching process is performed to lower the dopant concentration at the top surface. After this sputtering or chemical etching process, a traditional passivation process can be performed.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 21, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Cuiyang Wang, Timothy J. Miller, Jun Seok Lee, Il-Woong Koo, Deven Raj Mittal, Peter G. Ryan, Jr.
  • Patent number: 11127633
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of blowing out air to push up each device chip and picking up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: September 21, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11114307
    Abstract: A method of producing a wafer includes a peel-off layer forming step to form a peel-off layer in a hexagonal single-crystal ingot by applying a laser beam having a wavelength transmittable through the hexagonal single-crystal ingot while positioning a focal point of the laser beam in the hexagonal single-crystal ingot at a depth corresponding to the thickness of a wafer to be produced from an end face of the hexagonal single-crystal ingot, an ultrasonic wave generating step to generate ultrasonic waves from an ultrasonic wave generating unit positioned in facing relation to the wafer to be produced across a water layer interposed therebetween, thereby to break the peel-off layer, and a peel-off detecting step to detect when the wafer to be produced is peeled off the hexagonal single-crystal ingot by positioning an image capturing unit sideways of the wafer to be produced.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: September 7, 2021
    Assignee: DISCO CORPORATION
    Inventor: Ryohei Yamamoto
  • Patent number: 11101165
    Abstract: A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 24, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
  • Patent number: 11094683
    Abstract: A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin Wunsch, Joshua T. Smith, Stacey Gifford, Michael Albert Pereira
  • Patent number: 11088130
    Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, where the third layer includes crystalline silicon, and where the second level includes at least one phase-lock-loop (“PLL”) circuit.
    Type: Grant
    Filed: February 6, 2021
    Date of Patent: August 10, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11081668
    Abstract: A display device includes a substrate including a display area, a first non-display area surrounding the display area, and a second non-display area surrounded by the display area, a through portion disposed in the second non-display area, the substrate in the through portion being removed, and a first groove disposed in the second non-display area in the substrate to surround the through portion.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: August 3, 2021
    Inventors: Wooyong Sung, Hyoungsub Lee, Moonwon Chang
  • Patent number: 11075218
    Abstract: A method of making three-dimensional memory device includes forming a stack of insulating layers and silicon nitride sacrificial layers over a substrate, forming memory stack structures in the alternating stack, forming a trench through the alternating stack, selectively etching the silicon nitride sacrificial layers through the trench using a phosphoric acid solution, filling a sample container with a fixed quantity of the phosphoric acid solution that was used to etch the silicon nitride sacrificial layers, determining a weight of the sample container, determining if a threshold value indicative of the etching end point has been reached or exceeded based on the determined weight, stopping the etching of the silicon nitride sacrificial layers in response to determining that the threshold value indicative of the etching end point has been reached or exceeded to leave recesses between the insulating layers, and filling the recesses with electrically conductive layers.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: July 27, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Shigehisa Inoue
  • Patent number: 11069574
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyester sheet, pushing up each device chip through the polyester sheet, and then picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 20, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11060190
    Abstract: A controller that processes a substrate by executing a process recipe for supplying at least a source gas to a process chamber to form a film on the substrate, and a pressure controller that controls the degree of opening of a pressure control valve on the basis of a pressure value detected by a pressure sensor that detects a pressure in a furnace during execution of the recipe and maintains the process chamber to a predetermined pressure. The pressure controller includes a memory that accumulates data acquired from the pressure sensor and pressure control valve, and measures a valve full close time to full close of the pressure control valve during execution of the process recipe and holds the valve full close time in the memory, and the controller acquires the stored valve full close time and confirms whether the acquired valve full close time falls within a threshold range.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: July 13, 2021
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Kazuo Nakaya, Hiroki Okamiya
  • Patent number: 11056334
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of blowing air to each device chip through the polyester sheet to push up each device chip, thereby picking up each device chip from the polyester sheet after performing the dividing step.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: July 6, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11049757
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form division grooves in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of applying an ultrasonic wave to the polyester sheet in each region of the polyester sheet corresponding to each device chip, pushing up each device chip from the polyester sheet side to pick up each device chip from the polyester sheet.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: June 29, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 11049772
    Abstract: A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of picking up each device chip from the polyester sheet.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: June 29, 2021
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae