Abstract: Methods of forming line-end extensions and devices having line-end extensions are provided. In some embodiments, a method includes forming a patterned photoresist on a first region of a hard mask layer. A line-end extension region is formed in the hard mask layer. The line-end extension region extends laterally outward from an end of the first region of the hard mask layer. The line-end extension region may be formed by changing a physical property of the hard mask layer at the line-end extension region.

Abstract: An image sensor includes a first unit. The first unit includes a first photodiode having a first dimension, a second photodiode disposed adjacent the first photodiode and having a second dimension that is greater than the first dimension, a first color filter overlapping the first photodiode and the second photodiode, and a first internal reflector disposed in the first color filter and overlapping the first photodiode. The first internal reflector has an inclined light receiving surface inclined from a top surface of the first color filter toward the second photodiode, and a refraction index of the first internal reflector is smaller than a refraction index of the first color filter.

Abstract: A semiconductor package includes a base film having a first mount section, a first folding section, a second folding section, and a second mount section. A first semiconductor chip is disposed on the first mount section of the base film. A second semiconductor chip is disposed on the second mount section of the base film. Test pads are disposed on the first or second folding sections of the base film and is connected to each of the first and second semiconductor chips. Connection pads are disposed on the first or second mount sections of the base film and are connected to each of the first and second semiconductor chips. The first and second folding sections vertically overlap each other. The test pads are interposed between and buried by the first and second folding sections.

Abstract: An imaging element, includes a pixel array in which a plurality of pixels including photoelectric conversion elements are arranged in a two-dimensional array, and an optical element array in which optical elements composed of a plurality of columnar structure bodies arranged opposite to a pixel array and guiding incident light to a corresponding photoelectric conversion element are arranged in a two-dimensional array, wherein the plurality of columnar structure bodies are formed in a width having a phase characteristic for guiding light to a photoelectric conversion element directly below a columnar structure body in accordance with an incident angle of the incident light of each columnar structure body when viewed in a plan view and are formed at a same height when viewed in a side view.

Abstract: An image sensor includes a color unit pixel comprising sub-pixels arranged in an m×n matrix on a substrate, and a pixel isolation structure isolating the sub-pixels from each other in the color unit pixel. The pixel isolation structure includes an outer isolation film surrounding the color unit pixel, at least one inner isolation film including a portion between two sub-pixels, which are adjacent to each other, among the sub-pixels, a doped isolation liner covering opposite sidewalls of the at least one inner isolation film, and at least one doped isolation pillar contacting at least two sub-pixels selected from the sub-pixels. The at least one doped isolation pillar and the at least one inner isolation film are arranged to define a size of a partial region of each of the sub-pixels.

Abstract: Provided is a display substrate. The display substrate includes a base substrate which includes a first surface; a first transistor which includes a first active layer and a first gate insulative layer; a first insulative layer; and a second transistor which includes a second active layer and an orthographic projection of the second active layer on the first surface is staggered from an orthographic projection of the first active layer on the first surface.

Abstract: Disclosed is a magnetic field-free spin-orbit torque switching device including a sapphire miscut substrate. More particularly, a spin-orbit torque switching device according to an embodiment includes a substrate having a step-terrace structure; and an input device formed on the substrate and provided with a heavy metal layer HM and a ferromagnetic layer FM.

Abstract: A structure includes a first air gap including a first opening defined in a first dielectric layer and a second dielectric layer over the first opening and closing an end portion of the first opening. A second air gap may be over at least a portion of the first air gap. The second air gap includes a second opening defined in the second dielectric layer and a third dielectric layer over the second opening and closing an end portion of the second opening. The second air gap has a pointed lower end portion. In another version, the structure includes a first air gap in a first dielectric layer, a second dielectric layer over the first air gap, and a discrete dielectric member positioned in the second dielectric layer and aligned over the first air gap.

Abstract: An integrated circuit assembly may be fabricated to include an integrated circuit device having a backside surface and a metal matrix composite layer on the backside surface, wherein the metal matrix composite layer has a filler material disposed therein to reduce the coefficient of thermal expansion thereof. The filler material may be a plurality of graphitic carbon filler particles, wherein the plurality of graphitic carbon filler particles has an average aspect ratio of greater than about 10, or the filler material may be a plurality of diamond particles, wherein the filler material is clad with a metal material.

Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Abstract: The present feature relates to a solid-state imaging device that allows generation of flare to be reduced and a manufacturing method therefor. A solid-state imaging device according to the present feature includes a semiconductor substrate having a pixel area having a plurality of pixels provided therein, and a transparent structure joined to a light incident surface side of the semiconductor substrate with resin and having a hollow structure. In the solid-state imaging device according to the present feature, the transparent structure includes a glass substrate and a transparent film, and the hollow structure is formed between the glass substrate and the transparent film. The present feature can be applied for example to imaging devices.

Abstract: An integrated chip including includes a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a substrate, a first dielectric layer, a second dielectric layer, and a gate structure, where an active region is provided in the substrate, and a source region of a first doping type and a drain region of the first doping type are disposed in the active region; the first dielectric layer is disposed on the substrate and covers a part of the source region and/or a part of the drain region; the second dielectric layer is disposed on the substrate and connected to the first dielectric layer, a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer.

Abstract: An image sensor includes a color unit pixel comprising sub-pixels arranged in an m×n matrix on a substrate, and a pixel isolation structure isolating the sub-pixels from each other in the color unit pixel. The pixel isolation structure includes an outer isolation film surrounding the color unit pixel, at least one inner isolation film including a portion between two sub-pixels, which are adjacent to each other, among the sub-pixels, a doped isolation liner covering opposite sidewalls of the at least one inner isolation film, and at least one doped isolation pillar contacting at least two sub-pixels selected from the sub-pixels. The at least one doped isolation pillar and the at least one inner isolation film are arranged to define a size of a partial region of each of the sub-pixels.

Abstract: A light emitting display apparatus according to an aspect of the present disclosure may include a first driving transistor and a second driving transistor spaced apart from each other on a substrate, a first anode connected to the first driving transistor and overlapping with the second driving transistor, a second anode connected to the second driving transistor, and a shielding metal between the second driving transistor and the first anode. The second anode may have a smaller area than the first anode, and the shielding metal may reduce a parasitic capacitance associated with the second anode and the first anode.

Abstract: There is provided a solid-state imaging apparatus that allows to suitably dispose a translucent member on a substrate including a photoelectric conversion portion. The solid-state imaging apparatus of the present disclosure has: a substrate that includes a photoelectric conversion portion; a lens that is disposed on the substrate; and a translucent member that is disposed on the lens. The translucent member includes a plurality of protruded portions that are disposed in a two-dimensional array form on an upper surface of the translucent member.

Abstract: An imaging device includes: a semiconductor substrate in which multiple sensor pixels are arranged in array, the semiconductor substrate having a first surface serving as a light incident surface and a second surface opposed thereto; a photoelectric conversion section provided on a side of the first surface inside the semiconductor substrate and generating electric charge corresponding to a light reception amount by photoelectric conversion; a charge-holding section provided on a side of the second surface inside the semiconductor substrate and holding the electric charge transferred from the photoelectric conversion section; a first light-blocking section extending in an in-plane direction of the semiconductor substrate between the photoelectric conversion section and the charge-holding section; and a light-condensing optical system provided on the side of the first surface and condensing incident light on a substantial geometric center of the first light-blocking section in a plan view.

Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.

Abstract: An image sensor may include a sensor chip that is bonded to an application-specific integrated circuit (ASIC) chip. A bond pad for the image sensor may be formed in the ASIC chip and exposed through a trench in the sensor chip. The image sensor may include a conductive light shield at a periphery of the image sensor to shield optically black pixels. An opaque layer may be formed over the conductive light shield to mitigate reflections off the conductive light shield. An anti-reflective layer may be formed over the pixel array. The anti-reflective layer may have a different thickness over the pixel array than in the trench for the bond pad.

Abstract: An SGT MOSFET device and a manufacturing method of contact holes of the SGT MOSFET device relate to a field of power semiconductor device manufacturing. The manufacturing method includes steps of preparing a gate trench, source trenches, a shielding gate trench, and a pre-embedded ESD trench, preparing a cell structure, preparing an ESD region, a body region, and a source region by ion implantation and preparing a gate contact hole, a source contact hole, a shield gate contact hole, and ESD contact holes. By pre-embedding an ESD structure, depth differences between the gate contact hole, the source contact hole, the shielding gate contact hole, and the ESD contact holes are reduced, and the contact holes are prepared by only one photolithography process. The manufacturing method reduces one photolithography process and one process of growing ESD polysilicon, saves cost, and reduces difficulty of the manufacturing process.