Abstract: A computer-implemented computer shut-down method includes identifying that a computing device has been moved from an open configuration in which input and output mechanisms on the computing device are accessible to a user, to a closed configuration in which at least some of the input and output mechanisms are inaccessible to a user; starting a shut-down timer in response to identifying that the computing device has been moved from the open configuration to the closed configuration; waiting a predefined time period, as established by the shut-down timer, and determining from the shut-down timer that the computing device can be transitioned from an active state into a sleep state in which power consuming components of the computing device are powered down; and transitioning the computing device from the active state to the sleep state upon determining that the computing device can be transitioned.

Abstract: Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

Abstract: A USB Type-C module has a plurality of ground pins including a first ground pin, a first configuration pin, a second configuration pin and a detector. The detector is electrically connected to the first ground pin and configured to detect a voltage value at the first ground pin so as to selectively enable a controller to determine a configuration of a corresponding connector via at least one of the first configuration pin and the second configuration pin.

Abstract: Systems and methods for using host command data buffers as extended memory device volatile memory are disclosed. NVM Express implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. Commands may include an indication of a host buffer, resident on the host device, in which to store data for access by the host device. The memory device may use the host buffer as extended memory during execution of the command. As one example, the memory device may process the command in stages, with each stage retrieving data from the host buffer, manipulating the data, and writing the processed data to the same host buffer. As another example, the host buffer can be used for memory device internal relocation and garbage collection operations. Thus, the area/cost of the memory device controller is reduced since less volatile memory is required.

Abstract: The present disclosure provides a method and an apparatus for controlling a serial peripheral interface of a fingerprint sensor, and a mobile terminal. The method includes: detecting a fingerprint signal via a fingerprint sensor; and when the fingerprint signal is detected, opening the serial peripheral interface of the fingerprint sensor.

Abstract: Embodiments can provide additional computing resources at minimal and incremental cost by providing instances of one or more server compute subsystems on a system-on-chip. The system-on-chip can include multiple compute subsystems where each compute subsystem can include dedicated processing and memory resources. The system-on-chip can also include a management compute subsystem that can manage the processing and memory resources for each subsystem.

Abstract: New techniques for establishing communications connections for computer systems are provided. In some aspects, a new technique for rapidly establishing a uniform, secure wireless peripheral device network is provided. In some embodiments of the invention, the secure peripheral device network is activated by physical docking and/or interlocking, without any use of a wired network connection, based on precise proximity and location information. In other embodiments, a secure, encrypted peripheral device network is established by a system in response to terminating a wired network connection, easing the transition from wired to wireless connection status, and easing the creation of wireless networks. The resulting wireless networks may also be more secure than other forms of wireless networks, using a new form of physically-isolated negotiation for encryption keys, based on physical features and limits of a peripheral device interface.

Abstract: Out-of-band management of data drives including receiving, from a user, a control command targeting a data drive communicatively coupled to a backplane, wherein the data drive is communicatively coupled to the computing device via an interconnect bus; generating, based on the control command, an out-of-band command targeting a baseboard management controller (BMC) communicatively coupled to the backplane, wherein the out-of-band command comprises a data drive location identifier; sending the out-of-band command to the BMC, wherein the BMC, in response, identifies the data drive on the backplane using the data drive location identifier and a cable topology table, and performs the out-of-band command on the data drive; and receiving, from the BMC, a first notification that the out-of-band command has been performed on the data drive identified by the data drive location identifier.

Abstract: An example computing device includes a module interface to communicate with a peripheral device. The computing device also includes a hot swapping prediction circuit to detect a physical movement of the computing device and to generate a hot swapping prediction signal based on the detected physical movement. The computing device further includes a processor coupled to the hot swapping circuit. The processor is to, in response to detecting the hot swapping prediction signal from the hot swapping circuit, change a parameter of a peripheral device detection operation to be executed by an operating system of the computing device.

Abstract: In some examples, an electronic device is to receive a configuration setting that is configurable to a first setting to indicate a first mode of operation, and a second setting to indicate a second mode of operation, wherein a feature supported by the first mode of operation is disabled in the second mode of operation; and configure a dock to which the electronic device is connected to operate according to a mode indicated by the configuration setting.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: Systems and methods for integrated thermal management of storage drives are described. In one embodiment, the storage system device may include a storage enclosure, a plurality of storage drives enclosed in the storage enclosure, and one or more processors in each of the plurality of storage drives. In some cases, the plurality of storage drives may include a first storage drive and a second storage drive. In some embodiments, the one or more processors of the first storage drive may be configured to activate a drive temperature monitor of the first storage drive in response to a manufacturer specific command, detect a temperature event of the first storage drive, and send a notification to the storage enclosure upon detecting the temperature event, the notification indicating the temperature event.

Abstract: Introduced here are multi-server sleds that include multiple card slots for receiving modular cards. Pairs of card slots can be connected to one another via a Peripheral Component Interconnect Express (PCIe) bus. However, communication via the PCIe bus may only be permitted when the pair of card slots includes modular cards of different types (e.g., a server card and a device card). Card type can be established by looking at the voltage available on a single pin of the PCIe bus corresponding to a modular card, and/or parsing system information stored within a memory of the modular card. This is enabled by a baseboard management controller (BMC) that communicates with the modular card via a bridge integrated circuit (IC) interface. Software-implemented modifications to the standard PCIe pin assignments may be made to avoid permitting communication between modular cards of the same type.

Abstract: Embodiments of the technology can provide the flexibility of fine-grained dynamic partitioning of various compute resources among different compute subsystems on an SoC. A plurality of processing cores, cache hierarchies, memory controllers and I/O resources can be dynamically partitioned between a network compute subsystem and a server compute subsystem on the SoC.

Abstract: Provided are a communication device and a communication restriction program capable of suppressing invalid message transmission to a network by injecting an invalid program. The ECU includes a CAN controller having a register group storing a value concerning communication with a different ECU and a processing unit processing a value for the register group. The ECU switches the mode between the full control mode in which writing and reading are allowed for the register group in the CAN controller and the restriction mode wherein writing and reading are restricted for a part of the registers in the register group. The ECU sets a predetermined period from activation corresponding to the full control mode, and switches the full control mode to the restriction mode after the predetermined period elapses. After switching to the restriction mode, the ECU will not switch the mode to the full control mode.

Abstract: Systems and Methods are disclosed for providing measurement data redundancy to intelligent electronic devices (IEDs) in an electric power system, without additional redundant components. In various embodiments, a first measurement device obtains measurement data from a first portion of the electric power delivery system. A second measurement device obtains measurement data from a second portion of the electric power delivery system. A first IED monitors the first portion of the electric power delivery system based on measurement data associated with the first portion of the electric power delivery system, and a second IED monitors the second portion of the electric power delivery system based on measurement data associated with the second portion of the electric power delivery system.

Abstract: A host divides a dataset into stripes and sends the stripes to respective data chips of a distributed memory buffer system, where the data chips buffer the respective slices. Each data chip can buffer stripes from multiple datasets. Through the use of: (i) error detection methods; (ii) tagging the stripes for identification; and (iii) acknowledgement responses from the data chips, the host keeps track of the status of each slice at the data chips. If errors are detected for a given stripe, the host resends the stripe in the next store cycle, concurrently with stripes for the next dataset. Once all stripes have been received error-free across all the data chips, the host issues a store command which triggers the data chips to move the respective stripes from buffer to memory.

Abstract: A network interface controller includes a media access controller and a host adapter. The host adapter includes a transmit route connected to receive an in-band packet from a host and further connected to transmit the in-band packet to the media access controller. The network interface controller also includes a sideband port controller connected to receive a sideband packet destined for a network from a sideband endpoint and further connected to transmit the sideband packet to the host adapter. The host adapter further includes a host buffer to store the in-band packet, a sideband buffer to store the sideband packet, and an arbiter connected to allow, at different times, the in-band packet to advance along the transmit route from the host buffer to the media access controller and the sideband packet to advance along the transmit route from the sideband buffer to the media access controller.

Abstract: A device includes a USB-C controller instantiated as a first integrated circuit that includes a first set of host terminals coupled to host controllers and a second set of terminals coupled to sets of D+/D? terminals of a type-C receptacle. A D+/D? multiplexer is to selectively couple the first set of host terminals to the second set of terminals. An electrostatic discharge (ESD) protection circuit is coupled between the D+/D? multiplexer and the second set of terminals. A charger detector circuit is coupled between a positive data system terminal and a negative data system terminal of the first set of terminals, the charger detector circuit to detect whether the second set of terminals is coupled to a USB charger through the type-C receptacle.