Abstract: A peripheral interface multiplexing method. The method includes receiving, by using a first pin in a peripheral interface of user equipment, a coded signal sent by an external device, where the coded signal includes a first electrical characteristic value of the first pin; decoding the coded signal to obtain a decoded signal, where the decoded signal includes a control signal that corresponds to the first electrical characteristic value of the first pin, and the control signal is used to control the peripheral interface to transmit a target signal that a user requests to transmit; and controlling, according to the control signal, a pin that is in the peripheral interface and used for signal transmission to transmit the target signal. Therefore, communications interfaces of user equipment can be extended without increasing a quantity of peripheral interfaces, so that the user equipment provides more communications manners, and user experience is improved.

Abstract: Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

Abstract: An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.

Abstract: Computing device interface connectors for PCI compliant devices and other devices are disclosed. According to an aspect, an apparatus includes a PCI compliant device residing on a computing device. Further, the apparatus includes another device such as a network controller sideband interface (NCSI) compliant device residing on the computing device. The apparatus also includes an interface connector being communicatively connected to the PCI compliant device and the NCSI compliant device.

Abstract: Technology for identifying a device location in a system or network includes an example method comprising detecting, by a controller, a device being connected to a location of a set of locations connected to the controller. Responsive to detecting the device, the controller can assign a device identifier (ID) to the device. A device ID may be based on a set of component IDs corresponding to components associated with the device and a component ID may be a system ID, a first controller ID, a first port ID, a first bus ID, or an information ID associated with the device. Further, the device ID can identify the location where the device resides.

Abstract: A control unit provides a number of buffer credits, to one or more channels, in response to an initiation of a startup phase of communication between the one or more channels and the control unit, where the provided number of buffer credits when used for transferring data causes transfer ready operations but no retry operations. The control unit iteratively increases the number of buffer credits by an amount that is high enough to eliminate any transfer ready operations or cause retry operations to occur within a predetermined amount of time from the initiation of the startup phase.

Abstract: A hazard management system is provided with a field bus and a broadband bus. The field bus is configured to connect at least two units of the hazard management system for sending alarm signals among the units of a hazard management system. The broadband bus, which is separate from the field bus, is configured to connect at least two units of a hazard management system, so that these units may exchange data through the broadband bus. The broadband bus is configured to stream audio and/or video data from one unit to other units or to deploy software updates among the units of the hazard management system.

Abstract: A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.

Abstract: A method is described and in one embodiment includes monitoring by an integrated circuit device READ/WRITE commands in connection with a flow of an application executing in a Fiber Channel Storage Area Network (“FC-SAN”); determining from the monitored READ/WRITE commands at least one metric for characterizing I/O performance of the application with respect to a storage device, wherein the at least one metric includes at least one of an inter I/O gap (“IIG”), a Logical Unit Number (“LUN”) I/O access pattern (“IAP”), relative block size, I/O operations per second (“IOPS”) and throughput, and IOPS per virtual server; storing the calculated at least one metric in a flow record associated with the flow; and using the calculated at least one metric to identify a storage device for use by the flow, wherein the calculated at least one metric is indicative of a performance of the application in the FC-SAN.

Abstract: A data transmission method and a mobile terminal include taking bytes of data in universal asynchronous receiver/transmitter (UART) format generated by a mobile terminal, simulating UART ports via GPIO ports of a processor of the mobile terminal, and transmitting the bytes of data in UART format divided in batches to a receiving terminal via the GPIO ports. In transmitting the bytes of data in UART format in divided batches to the receiving terminal via the GPIO ports, the processor of the mobile terminal is in a locked state. The processor is in an unlocked state between two adjacent batches of the data transmitting.

Abstract: A method for actively initiating a connection to and communicating with an Apple device via USB, relating to the field of communications, and comprising: an Apple device attachment, when detecting access by a USB device, determines whether the accessing USB device is an Apple device (S1); the Apple device attachment establishes a device address for the Apple device (S2); the Apple device attachment acquires the current communication protocol setup of the Apple device, and determines whether the current communication protocol configuration of the Apple device is a preset configuration (S3); the Apple device attachment sets the current communication protocol configuration of the Apple device as the preset configuration (S4); the Apple device attachment notifies the Apple device to register the Apple device attachment to the Apple device (S5); the Apple device attachment establishes a connection with the Apple device (S6); the Apple device attachment periodically queries whether communication data has been sent

Abstract: Various examples described herein provide for a management processor that reads a registration script from a peripheral device, and uses the script to act in proxy to register the peripheral device as a data provider on the management processor. Once a peripheral device is registered as a data provider on the management processor, the management processor can permit the peripheral device to host a management resource on the management processor. By accessing the hosted management resource through the management processor, a client can manage, monitor, or control the peripheral device.

Abstract: A computational device maintains a spinlock for exclusive access of a resource by a process of a plurality of processes. In response to determining by the process that a turn for securing the spinlock has not arrived for the process, a sleep duration is determined for the process, prior to making a next attempt to secure the spinlock.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.

Abstract: An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively.

Abstract: A data transfer device of a display equipment and a data transfer method are provided. The data transfer device of the display equipment includes a display panel, a first transfer connector, a second transfer connector, a configuration switch and a control unit. The first and the second transfer connector are in line with a universal serial bus (USB) protocol including a plurality of data paths. When a first electronic device is connected to the first transfer connector, the control unit separates the data paths of the first transfer connector into at least one video data path and at least one data-transferring data path dynamically. A video signal of the first electronic device is transferred to the display panel through the video data path, and the first electronic device and the second electronic device transfer data to each other through the data-transferring data path.

Abstract: The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a physical layer output signal according to a serializer/deserializer (SerDes) reception signal; an input/output (I/O) circuit operable to generate at least one terminal output signal according to signal variation of at least one terminal; and a processing circuit operable to make the solid state drive control device adapt to one of several interface types in accordance with the physical layer output signal and/or the at least one terminal output signal.

Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

Abstract: Techniques for low-power USB Type-C receivers with high DC-level shift tolerance are described herein. In an example embodiment, a USB-enabled device comprises a receiver circuit coupled to a Configuration Channel (CC) line of a USB Type-C subsystem. The receiver circuit is configured to receive data from an incoming signal on the CC line even when the incoming signal has more than 250 mV of DC offset with respect to local ground, and to operate in presence of a VBUS charging current that is specified in a USB-PD specification.