Abstract: A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Abstract: Enabling parallel memory accesses by providing explicit affine instructions in vector-processor-based devices is disclosed. In this regard, a vector-processor-based device implementing a block-based dataflow instruction set architecture (ISA) includes a decoder circuit configured to provide an affine instruction that specifies a base parameter indicating a base value B, a stride parameter indicating a stride interval value S, and a count parameter indicating a count value C. The decoder circuit of the vector-processor-based device decodes the affine instruction, and generates an output stream comprising one or more output values, wherein a count of the output values of the output stream equals the count value C. Using an index X where 0?X<C, each Xth output value in the output stream is generated as a sum of the base value B and a product of the stride interval value S and the index X.

Abstract: An example method of sharing message-signaled interrupt vectors in multi-processor computer systems comprises: associating an interrupt vector with a first device component, by creating a first interrupt mapping entry of an interrupt mapping table, wherein the first interrupt mapping entry references a first processor and the interrupt vector; associating the interrupt vector with a second device component, by creating a second interrupt mapping entry of the interrupt mapping table, wherein the second interrupt mapping entry references a second processor and the interrupt vector; and creating, in an interrupt descriptor table (IDT) associated with the first processor and the second processor, an interrupt descriptor for the interrupt vector.

Abstract: A network interface controller includes a media access controller and a host adapter. The host adapter includes a transmit route connected to receive an in-band packet from a host and further connected to transmit the in-band packet to the media access controller. The network interface controller also includes a sideband port controller connected to receive a sideband packet destined for a network from a sideband endpoint and further connected to transmit the sideband packet to the host adapter. The host adapter further includes a host buffer to store the in-band packet, a sideband buffer to store the sideband packet, and an arbiter connected to allow, at different times, the in-band packet to advance along the transmit route from the host buffer to the media access controller and the sideband packet to advance along the transmit route from the sideband buffer to the media access controller.

Abstract: A scalable, high-bandwidth connectivity architecture for portable storage devices and memory modules may utilize EHF communication link chip packages mounted in various two-dimensional and three-dimensional configurations on planar surfaces such as printed circuit boards. Multiple electromagnetic communication links between devices distributed on major faces of card-like devices may be provided with respectively aligned pairs of communication units on each device. Adjacent communication units on a printed circuit board may transmit or receive electromagnetic radiation having different polarization, such as linear or elliptical polarization. Power and communication between communication devices may both be provided wirelessly.

Abstract: A processor applies offset values to read and write pointers to a first-in-first-out buffer (FIFO) for data being transferred between clock domains. The pointer offsets are based on a frequency ratio between the clock domains, and reduce latency while ensuring that data is not read by the receiving clock domain from an entry of the FIFO until after the data has been written to the entry, thereby reducing data transfer errors. The processor resets the pointer offset values in response to a change in clock frequency at one or both of the clock domains, allowing the processor to continue to accurately transfer data in response to clock frequency changes.

Abstract: A baseboard management controller (BMC) includes a plurality of device I2C interfaces. Each device I2C interfaces provides a device I2C bus that is ported externally to the BMC. The BMC further includes a plurality of device buffer/switch circuits. Each device buffer/switch circuit is connected to a respective device I2C bus, and is configured to selectably connect to the respective I2C bus in a high-impedance mode, an open-drain mode, and a FET switch mode. The BMC further includes a multiplexor/driver circuit that has a multiplexor I2C interface that provides a multiplexor I2C bus that is ported externally to the BMC. The multiplexor/driver circuit is coupled to each device I2C bus via the respective buffer/switch circuit, and is configured to selectively couple one of the device I2C busses to the multiplexor I2C bus, and to select one of the high-impedance mode, the open-drain mode, or the FET switch mode for the selected buffer/switch circuit.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be an embedded-system device. The embedded-system device provides to a host of the embedded-system device control of a first serial port controller of the embedded-system device. The embedded-system device further connects a serial port with the first serial port controller. The embedded-system device also determines whether the embedded-system device is in a predetermined condition. The embedded-system device disconnects the serial port from the first serial port controller and connecting the serial port with a second serial port controller when the embedded-system device is in the predetermined condition.

Abstract: Provided is an in-vehicle control device that allows the giving and receiving of data via inter-core communication at the timing of a user, as well as being capable of minimizing processing load while satisfying safety requirements of different functional safety levels in the inter-core communication of a multicore microcomputer. The data communication between a plurality of cores is performed by a writing means for writing the data of a core register into a region of a shared memory of the cores, where safety levels are set, using a hardware function. The cores have different functional safety levels.

Abstract: A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that manages in what order a plurality of hardware threads are processed with a pre-established schedule, and an interrupt controller that receives an input interrupt request signal and assigns the interrupt request to an associated hardware thread, wherein the interrupt controller comprises a register in which information is stored for each channel of an interrupt request signal, and the information includes information regarding to which one or more than one of the plurality of hardware threads the interrupt request signal is associated.

Abstract: Embodiments described herein relate to circuits and techniques for interfacing a microprocessor with memory devices, particularly memory devices such as DDR SDRAM in accordance with protocols such as DDR4 and DDR5. Some embodiments particularly relate to a receiver architecture for a DDR memory interface device that provides AC coupling to memory and includes auto-zeroing functionality. These and other embodiments incorporate equalization functionality such as decision feedback equalization and continuous time linear equalization.

Abstract: Embodiments can provide additional computing resources at minimal and incremental cost by providing instances of one or more server compute subsystems on a system-on-chip. The system-on-chip can include multiple compute subsystems where each compute subsystem can include dedicated processing and memory resources. The system-on-chip can also include a management compute subsystem that can manage the processing and memory resources for each subsystem.

Abstract: One embodiment provides an apparatus. The apparatus includes a sensor module. The sensor module includes a sensor; and a sensor controller. The sensor controller is to enumerate the sensor to a sensor processing unit in response to being powered on. The enumerating includes communicating enumeration data to the sensor processing unit. The enumeration data includes one or more of a sensor name, a sensor manufacturer name, a sensor serial number, a hardware version, a firmware version, and/or one or more sensor characteristics. The sensor controller is further to monitor operation of the sensor and to provide sensor lifecycle information to the sensor processing unit over the lifecycle of the sensor.

Abstract: A FIFO memory device has a first number of data storage units and a second number of internal FIFO memories. Each internal FIFO memory has a third number of internal data storage units. The first number is a product of the second and third numbers. A fourth number of data inputs receives input data units in order. Input multiplexer circuitry connects each one of the data inputs to any one of the internal FIFO memories, for storage of input data units, in order, in a first layer of the FIFO memory device including corresponding storage locations in respective ones of the internal FIFO memories. The first layer may be physical, or may be logical and maintained by pointers. Output multiplexer circuitry coupled to the internal FIFO memories connects each of the internal FIFO memories to any one of the data outputs to read out the stored data units in order.

Abstract: Systems and methods for controlling multi-function general purpose input/output (GPIO) pins in a management controller stack, such as a baseboard management controller (BMC) stack. The system includes a management controller, which includes multiple pins. The management controller provides multiple functionalities, and each of the functionalities is related to at least one of the pins. In operation, the management controller provides a graphic user interface, which shows the functionalities, allowing the user to input an instruction to select one of the functionalities. Upon receiving the selected functionality, for each of the pins related to the selected functionality, the management controller sets a value of a corresponding register to indicate a functional status of the pin, such that the pins may provide the selected functionality based on the value of the corresponding registers.

Abstract: A single-ended receiver is coupled to an input-output (I/O) pin of a command and address (CA) bus. The receiver is configurable with dual-mode I/O support to operate the CA bus in a low-swing mode and a high-swing mode. The receiver is configurable to receive a first command on the I/O pin while in the high-swing mode, initiate calibration of the slave device to operate in the low-swing mode in response to the first command, switch the slave device to operate in the low-swing mode while the CA bus remains active, and to receive a second command on the I/O pin while in the low-swing mode.

Abstract: A computer-implemented computer shut-down method includes identifying that a computing device has been moved from an open configuration in which input and output mechanisms on the computing device are accessible to a user, to a closed configuration in which at least some of the input and output mechanisms are inaccessible to a user; starting a shut-down timer in response to identifying that the computing device has been moved from the open configuration to the closed configuration; waiting a predefined time period, as established by the shut-down timer, and determining from the shut-down timer that the computing device can be transitioned from an active state into a sleep state in which power consuming components of the computing device are powered down; and transitioning the computing device from the active state to the sleep state upon determining that the computing device can be transitioned.

Abstract: Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.

Abstract: In a memory system an interface circuit includes an interface to a memory array, and to a data signal. The circuit includes loopback circuitry to enable loopback of received data signals without having to access the data from the memory array. The circuit can be part of a memory device, a register device, or a data buffer. The circuit interfaces to a memory array of a memory device, and performs loopback functions for a host controller that can test the operation of the interface.

Abstract: A USB Type-C module has a plurality of ground pins including a first ground pin, a first configuration pin, a second configuration pin and a detector. The detector is electrically connected to the first ground pin and configured to detect a voltage value at the first ground pin so as to selectively enable a controller to determine a configuration of a corresponding connector via at least one of the first configuration pin and the second configuration pin.