Abstract: A system includes an input/output adapter operable to receive a plurality of packets in a single clock cycle. The system includes a controller operatively connected to the input/output adapter. The controller is operable to receive a first packet at a data link layer and determine a state of a first output indicator to maintain packet ordering. Based on determining that a first receiver formatting interface is selected by the first output indicator, the controller performs an alignment adjustment and output of the first packet by the first receiver formatting interface. Based on determining that a second receiver formatting interface is selected by the first output indicator, the controller performs the alignment adjustment and output of the first packet by the second receiver formatting interface.

Abstract: In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.

Abstract: A pattern-based service bus includes a plurality of bus endpoints, a bus-hosted service, and a bus storage component. The plurality of bus endpoints interact with bus participants external to the pattern-based service bus, wherein each of the plurality of bus endpoints are identified by a unique address, and type of interaction to be provided by the bus endpoint. The bus-hosted service implements patterns that define allowed interactions between each of the plurality of bus endpoints and the bus-hosted service, wherein the implemented patterns can be utilized by the plurality of bus endpoints to interact with the bus-hosted service. The bus storage component interacts with the bus-hosted service to store information relevant to operation of the pattern-based service bus.

Abstract: A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the clock error may be mitigated by maintaining a saturated state of a device. Furthermore, a register may be connected to a microcontroller and/or a graphical processing unit to negotiate control of a switch and a bus.

Abstract: A removable electronic module usable with an electrical system includes a main body, electronic devices, indicators, and a switching member. The indicators receive the power by the power storage device when the main body is removed from a slot and electrically disconnected from the electrical system to indicate a functional status of the corresponding electronic devices when placed in an active state.

Abstract: Multiple hardware and/or software components across the host and data storage system may be capable of performing data transformation operations. In at least one embodiment, a particular one of the multiple components may be selected, per I/O operation and using information generated by a component selection tool, to perform a data transformation operation. For an I/O operation, a first component may be selected to perform a first data transformation operation and a second different component may be selected to perform a second data transformation operation. The first and second components may both be on the host, both on the data storage system, or on different ones of the host and data storage system. A host I/O driver may create a request for the I/O operation where the request includes indicators identifying the first and second components as selected for performing the data transformation operations.

Abstract: A method includes communicating between at least first and second devices over a bus in accordance with a bus address space, including providing direct access over the bus to a local address space of the first device by mapping at least some of the addresses of the local address space to the bus address space. In response to indicating, by the first device or the second device, that the second device requires to access a local address in the local address space that is not currently mapped to the bus address space, the local address is mapped to the bus address space, and the local address is accessed directly, by the second device, using the mapping.

Abstract: Device identification generation in electronic devices to allow external control, such as selection or reprogramming, of device identification for bus communications identification, is disclosed. In this manner, device identifications of electronic devices coupled to a common communications bus in a system can be selected or reprogrammed to ensure they are unique to avoid bus communications collisions. In certain aspects, to select or reprogram a device identification in an electronic device, an external source can be electrically coupled to the electronic device. The external source closes a circuit with a device identification generation circuit in the electronic device. The closed circuit provides a desired electrical characteristic detectable by the device identification generation circuit. The device identification generation circuit is configured to generate a device identification as a function of the detected electrical characteristics of the closed circuit from the external source.

Abstract: Systems and methods for using host command data buffers as extended memory device volatile memory are disclosed. NVM Express implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. Commands may include an indication of a host buffer, resident on the host device, in which to store data for access by the host device. The memory device may use the host buffer as extended memory during execution of the command. As one example, the memory device may process the command in stages, with each stage retrieving data from the host buffer, manipulating the data, and writing the processed data to the same host buffer. As another example, the host buffer can be used for memory device internal relocation and garbage collection operations. Thus, the area/cost of the memory device controller is reduced since less volatile memory is required.

Abstract: In accordance with an embodiment, a method of operating a charging port having a power connection and a first data connection includes determining whether a compatible device is coupled to the charging port and receiving a serial data stream from the compatible device via the first data connection. The serial data stream includes a plurality of symbols representing a request for a power supply voltage and/or current, and the method further includes applying the requested power supply voltage and/or current to the power connection.

Abstract: There is provided a peripheral management system including a client terminal which a peripheral can be connected to and a management device which manages the peripheral, wherein: the client terminal comprises: a detection unit configured to detect an operating state of the connected peripheral; and a notification unit configured to notify the management device of the operating state detected by the detection unit at a predetermined communication interval; the management device comprises a storage unit configured to store the operating state of the peripheral notified by the notification unit; and the notification unit of the client terminal communicates with the management device at a longer communication interval than that when the peripheral to be managed is connected to the client terminal, when the peripheral to be managed is not connected to the client terminal.

Abstract: A transmitter is coupled to a command and address (CA) bus. The transmitter is configurable with dual-mode support to send commands over the CA bus in a first swing mode and a second swing mode. The transmitter is configurable to send a first command over the CA bus via the pins while in the first swing mode, initiate calibration of the master device to send commands over the CA bus in the second swing mode, and to send a second command over the CA bus via the pins while in the second swing mode.

Abstract: A manufacturing equipment digital interface includes a shared Small Computer Standard Interface (SCSI) connector that is electrically connected to a manufacturing equipment SCSI bus. A plurality of SCSI-to-target-memory bridges is electrically connected to the shared SCSI connector. The plurality of SCSI-to-target-memory bridges interfaces the shared SCSI connector to a plurality of target memory devices. A drive controller includes a memory buffer that provides temporary storage of the information being transferred from the manufacturing equipment SCSI bus to the plurality of target memory devices. Also, the drive controller includes a SCSI-to-target-memory bridge arbitrator that controls the transfers of information from the manufacturing equipment SCSI bus to the target memory device. A network interface is electrically connected to the drive controller.

Abstract: A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Abstract: Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design comprising one or more slaves configured to receive transaction requests from a plurality of masters. The data structure includes one or more counters for keeping track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions for each master using the one or more counters; and control logic that verifies that a transaction response for an in-flight transaction for a particular master has been issued by the slave in a predetermined order based on the tracked age for the in-flight transaction in the table.

Abstract: A control unit provides a number of buffer credits, to one or more channels, in response to an initiation of a startup phase of communication between the one or more channels and the control unit, where the provided number of buffer credits when used for transferring data causes transfer ready operations but no retry operations. The control unit iteratively increases the number of buffer credits by an amount that is high enough to eliminate any transfer ready operations or cause retry operations to occur within a predetermined amount of time from the initiation of the startup phase.

Abstract: Systems and methods for transmitting inter-processor interrupt messages by privileged virtual machine functions. An example method may comprise: mapping, by a hypervisor being executed by a processing device of a host computer system, a plurality of interrupt controller registers of the host computer system into a memory address space of a virtual machine being executed by the host computer system; mapping, into the memory address space of the virtual machine, a task mapping data structure comprising a plurality of records, each record associating a task with a processor of the host computer system; and mapping, into the memory address space of the virtual machine, a notification code module to be invoked by the virtual machine for writing a notification message into an interrupt controller register associated with a processor identified using the task mapping data structure.

Abstract: A method is described, for use in a data processing system, the system having a node and a communication link, wherein the communication link is coupled to the node. The method can comprise obtaining first digital signal information associated with a first signal, transmitting the first signal from the node to the communication link, receiving a second signal from the communication link at the node, and analyzing the second signal to obtain second digital signal information. The method can further include combining first digital signal information with second digital signal information and flagging a combination outside a predetermined condition space. Further, an apparatus, for use in the data processing system is described that can be operative to perform the method. A data processing system is also described.

Abstract: Systems and methods for sharing message-signaled interrupt vectors in multi-processor computer systems. An example method may comprise: associating an interrupt vector with a first device component; associating the interrupt vector with the second device component; creating, in a first interrupt descriptor table (IDT) associated with a first processor, a first interrupt descriptor to reference a first interrupt service routine to process a first interrupt triggered by the first device component; and creating, in a second IDT associated with a second processor, a second interrupt descriptor to reference a second interrupt service routine to process a second interrupt triggered by the second device component, wherein the first interrupt descriptor and the second interrupt descriptor reference the interrupt vector.

Abstract: A method and an apparatus for controlling an interrupt in a portable terminal are provided. The method includes executing an application based on user's control, determining whether an event occurs during the application execution, displaying information representing the event occurrence on a screen while continuing the application execution, and determining whether to interrupt the application by the event based on user's control.