Abstract: A power management system for managing power consumption of a digital signal processor (DSP) that implements a protection system, the power management system comprising: a power management block configured to: detect a parameter indicative of a power of an input signal to the DSP; compare the detected parameter to a threshold; and responsive to a determination that the detected parameter is less than the threshold, cause one or more processing blocks of the DSP to enter a low power mode of operation.

Abstract: An implementation of portable playback device power management involves launching a power coordinator background process, the power coordinator background process having multiple client programs and establishing respective inter-process communication (IPC) mechanisms between the multiple client programs and the power coordinator background process. The implementation further involves receiving, via the established IPC mechanisms from the multiple client programs, messages indicating that the respective client program is ready to suspend, and determining that each client program of the multiple client programs is ready to suspend. The implementation further includes sending instructions to the operating system to kernel suspend. While in kernel suspend, the playback device detects a particular trigger to kernel resume and in response, performs a kernel resume.

Abstract: A status monitoring system includes a status sensor configured to monitor a status of an electronic circuit. If the status monitoring system detects a status that exceeds a threshold, the status monitoring system records the details of the event on the electronic circuit. The status monitoring system operates in a low-power power mode during transit from a manufacturing facility to an installation location.

Abstract: Embodiments of the present application provide a power supply control method and apparatus of a server, and a power support unit of a server. The method includes: obtaining a target power supply power of a server to be powered; selecting, from a plurality of voltage converters deployed in a power support unit, one or more target voltage converters matched with the target power supply power; and controlling the one or more target voltage converters to supply power to the server, wherein each target voltage converter is configured for converting a power supply voltage of a power supply into a power supply voltage of the server. According to the present application, the problem in related art of low power supply efficiency of the power support unit can be solved, and the effect of improving the power supply efficiency of the power support unit is achieved.

Abstract: A system, method, apparatus and device for adjusting power consumption, and a medium are provided. The system includes a Power Supply Unit (PSU) and a Complex Programmable Logic Device (CPLD). An input end of the PSU is connected to a server, and the PSU is configured to receive an initial electrical signal of the server in real time, and determine a current power supply condition according to the initial electrical signal to obtain a final electrical signal. The CPLD is connected to an output end of the PSU, and the CPLD is configured to receive the final electrical signal, increase a power of the server when the final electrical signal is a signal representing that the current power supply condition is high output power, and decrease the power of the server when the final electrical signal is a signal representing that the current power supply condition is low output power.

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

Abstract: A method is presented for selectively throttling subsystems of a battery-powered computing device. The method comprises determining an amount of power consumed a plurality of rest-of-platform (ROP) subsystems of the battery-powered computing device. A total amount of power consumed by subsystems of a battery-powered computing device is determined. The subsystems including at least a system on a chip (SOC) and the plurality of ROP subsystems. Responsive to recognizing a condition where the amount of power consumed by the plurality of ROP subsystems is above an ROP power threshold, and where the total amount of power consumed increases above a first throttling threshold, one or more ROP subsystems are throttled.

Abstract: Performance adaptation for an integrated circuit includes receiving, by a workload prediction system of a hardware processor, telemetry data for one or more systems of the hardware processor. A workload prediction is determined by processing the telemetry data through a workload prediction model executed by a workload prediction controller of the workload prediction system. A profile is selected, from a plurality of profiles, that matches the workload prediction. The selected profile specifies one or more operating parameters for the hardware processor. The selected profile is provided to a power management controller of the hardware processor for controlling an operational characteristic of the one or more systems.

Abstract: A distributed power control system is provided that can include a datacenter and a remote master control system. The datacenter can include (i) computing systems, (ii) a behind-the-meter power input system configured to receive power from a behind-the-meter power source and deliver power to the computing systems, and (iii) a datacenter control system configured to control the computing systems and the behind-the-meter power input system. The remote master control system can be configured to issue instructions to the datacenter that affect an amount of behind-the-meter power consumed by the datacenter. The datacenter control system can receive, from a local station control system configured to at least partially control the behind-the-meter power source, a directive for the datacenter to ramp-down power consumption, and in response to receiving the directive, cause the computing systems to perform a set of predetermined operations correlated with the directive.

Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances.

Abstract: A computer system, computer readable storage medium, and computer-implemented method for detecting if one or more processing devices have separately sourced power feeds. The method includes determining transmission of a first signal in a first electric path. The method also includes monitoring for a second signal in a second electric path that is different from the first electric path. The method further includes determining, subject to the monitoring, electrical isolation between the first electric path and the second electric path. The claimed computer-implemented method dynamically, and automatically, determines that power sources are separate, isolated, and redundant.

Abstract: Methods and apparatus for performing timed functions in battery-powered, wireless electronic devices, such as sensors or control modules. Such electronic devices comprise a main processor and a co-processor. When the main processor enters a quiescent state in order to preserve battery life, one or more timed functions are transferred from the main processor to the co-processor just before the main processor enters the quiescent state. When the co-processor determines that it is time to perform the timed function, the co-processor wakes the main processor in order for the main processor to perform the timed function.

Abstract: A processing method includes responding to a trigger condition being satisfied, starting a first application, and controlling the first application to perform a target operation corresponding to a target request to implement a first function different from a second function. The first application runs in a pre-operating system environment. The second function includes a function for initializing the pre-operating system environment. Data used to implement the first function and the second function is stored in different storage locations.

Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.

Abstract: Systems and methods for performance tuning a computer system in scaling domains based on quantified scalability. A system includes a processor configured to: calculate an estimate of parallel fraction and speedup characteristic in a first domain D1 and in a second domain D2 for an application, the estimate being calculated using system performance measurements generated from previous processing iterations of one or more workloads of the application using a number, n, of cores in the first domain and a remaining number, N?n, of cores in the second domain to obtain performance values XD1(n) and XD2(N?n), wherein N represents a total number of cores; calculate the number of cores for the first domain using a quadratic equation generated from the parallel fraction and performance value in each domain; and execute the application in each domain using the number of cores for each domain.

Abstract: A processor may be in communication with a mining machine having a plurality of hash boards each including a plurality of mining chips. The processor may execute instructions that cause the processor to perform establishing communication with an external device via an external network, retrieving at least one profit variable from the external device via the external network, calculating an estimated profitability of at least a first mining chip of the plurality of mining chips as a function of at least a hashrate of at least the first mining chip, a power consumption of at least the first mining chip, and the at least one profit variable; and sending a command that causes the mining machine to adjust a chip voltage supplied to at least the first mining chip and adjusting a chip frequency of at least the first mining chip to maximize the estimated profitability.

Abstract: An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

Abstract: According to aspects of the present disclosure, a system, method, and storage medium comprising a plurality of sensors communicatively coupled to a microcontrol unit (MCU) wherein the MCU controls the transition between operational states. The MCU receives a system-related datum from one of the plurality of sensors. The MCU determines a control action based on the system-related datum. The MCU executes the control action on the system. The MCU sends a state change datum to a firmware wherein the state change datum indicates an operational change of the system based on the control action.

Abstract: A device includes a hardware block to perform a hardware process and internal logic coupled between a processing device, which executes instructions, and the hardware block. The internal logic can one of measure execution time or count clock cycles of at least a portion of the hardware process. The internal logic can further, in response to the measured execution time or the counted clock cycles satisfying a predetermined condition, provide data associated with the one of the execution time measurement or the clock cycles count to the processing device, the data being statistically indicative of a latency of data packets sent by the hardware process over a total time the hardware process executes.

Abstract: The present application describes a power management system for controlling delivery of power to a plurality of processing elements. The power management system includes a plurality of power management circuits arranged between terminals of a power supply. Each power management circuit is configured to connect to a processing element of the plurality of processing elements, and either supply sufficient power to power processing at the processing element, or prevent supply of sufficient power to power processing at the processing element. The power management system includes one or more power controllers arranged to determine whether or not to supply sufficient power to a processing element of the plurality of processing elements to perform processing.