Abstract: It is an object of the present disclosure to improve robustness against an unintended alteration in data in a volatile memory. An information processing apparatus has a storage unit storing two or more boot programs; a determination unit configured to determine the validity of each of the boot programs; an information generation unit configured to generate volatile information; and a selection unit configured to extract the volatile information at random, selects one of the boot programs on a basis of the extracted volatile information, and in a case where the determination unit determines that the selected boot program is not valid and that another one of the boot programs is valid, perform a process of overwriting the selected boot program with the another boot program.

Abstract: A computing device and method controls power consumption of a graphics processing unit in the computing device by the GPU determining an allocated power for the USB device connected through a USB port, such as a USB-C port. The GPU issues allocated power information for the external USB device to cause the allocated power to be provided to the USB device and includes issuing allocated power information to a power delivery (PD) controller that is connected to a USB port. In some implementations, the GPU shifts at least a portion of the allocated power from the USB device back to the GPU in response to a usage change event associated with the USB device for improving GPU performance. The usage change event can be a disconnect event of the USB device, a power renegotiation event between the USB device and the GPU, or any other suitable usage change event.

Abstract: Example techniques related to portable playback device power management. An example implementation involves launching a power coordinator background process, the power coordinator background process having multiple client programs and establishing respective inter-process communication (IPC) mechanisms between the multiple client programs and the power coordinator background process. The implementation further involves receiving, via the established IPC mechanisms from the multiple client programs, messages indicating that the respective client program is ready to suspend, and determining that each client program of the multiple client programs is ready to suspend. The implementation further includes sending instructions to the operating system to kernel suspend. While in kernel suspend, the playback device detects a particular trigger to kernel resume and in response, performs a kernel resume.

Abstract: Obtaining a periodic test signal, sampling the periodic test signal using a sampling element according to a sampling clock to generate a sampled periodic output, the sampling element operating according to a supply voltage provided by a voltage regulator, the voltage regulator providing the supply voltage according to a supply voltage control signal, comparing the sampled periodic output to the sampling clock to generate a clock-to-Q measurement indicative of a delay value associated with the generation of the sampled periodic output in response to the sampling clock, generating the supply voltage control signal based at least in part on an average of the clock-to-Q measurement, and providing the supply voltage to a data sampling element connected to the voltage regulator, the data sampling element being a replica of the sampling element, the data sampling element sampling a stream of input data according to the sampling clock.

Abstract: Controlling power consumption at an IHS, including receiving electrical power associated with an initial voltage at a first time; determining that the IHS is to enter a low-power state, and in response: adjusting an UVP parameter for the electrical power from a first voltage to a second voltage, the second voltage less than the first voltage, the second voltage based on the low-power state; adjusting an OCP parameter for the electrical power from a first amperage to a second amperage, the second amperage less than the first amperage, the second amperage based on the low-power state; trimming the initial voltage of the electrical power to a trimmed voltage, the trimmed voltage less the initial voltage and greater than the second voltage; adjusting the power state of the IHS to the low-power state; receiving the electrical power having the trimmed voltage at a second time after the first time.

Abstract: Systems and methods are provided for automated and distributed configuration of platform deployments on remote computing devices, such as laptop computers. The platform deployments can include services that mirror that of a server-based platform deployment. A centralized entity be used to generate and/or edit a single configuration file that contains multiple subset configuration files, each corresponding to a service to be deployed to each of the remote computing devices. The configuration file can be customized for the remote computing devices. Additionally, interaction between services can be achieved by using a templating language that allows certain aspects of the configuration file to include references to values.

Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.

Abstract: Provided is a safety control method for an AI server, which is applied in an FPGA. The method includes: obtaining a current electrical current and a current power of a GPU in the AI server according to a preset frequency; determining whether the GPU satisfies a first control privilege transfer requirement; when the GPU satisfies the first control privilege transfer requirement, taking over control privilege of a heat dissipation system from a BMC; and controlling the heat dissipation system according to the current electrical current and the current power of the GPU; wherein the first control privilege transfer requirement includes: the current electrical current of the GPU exceeds a preset electrical current, or a rate of change of the current electrical current of the GPU exceeds a preset rate of change of electrical current, or the current power of the GPU exceeds a first preset power.

Abstract: Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event.

Abstract: A clock calibration module, a high-speed receiver, and an associated calibration method are provided. The calibration method is applied to the high-speed receiver having the clock calibration module and a sampler. The sampler samples an equalized data signal with a sampler-input clock. The clock calibration module includes multiple clock generation circuits and a clock calibration circuit. Each of the clock generation circuits includes a phase interpolator, a duty cycle corrector, and a phase corrector. In a calibration mode, the phase interpolator interpolates a reference input clock and generates an interpolated clock accordingly. The duty cycle corrector generates a duty cycle corrected clock based on the interpolated clock. The phase corrector generates the sampler-input clock based on the duty cycle corrected clock. The phase interpolator is controlled by a phase interpolator calibration signal, and the phase corrector is controlled by a phase corrector calibration signal.

Abstract: The invention relates to a multi-phase power supply regulator and a temperature balance control method thereof. The method comprises: providing a multi-phase power supply regulator which includes a controller and a plurality of power stages, transmitting a plurality of control signals to the plurality of power stages respectively by the controller. Each of the plurality of power stages includes a temperature sampling unit, wherein outputs of the temperature sampling units are connected in parallel and the plurality of power stages outputs a temperature detection signal. The invention determines one of the plurality of power stages comprising highest temperature by sequentially adjusting the control signals, the temperature of the power stage is reduced, and the temperatures of the multi-phase power supply regulator are balanced.

Abstract: Systems, methods, and computer-readable media are disclosed for a systems and methods for improved LIDAR return light capture efficiency. One example method may include comparing, by a controller including a processor and at a first time, a first temperature of a first computing element to a first threshold temperature and a second temperature of a second computing element to a second threshold temperature. The example method may also include sending, based on a determination that the first temperature is below the first threshold temperature and the second temperature is above the second threshold temperature, a first signal to a switch to activate a data output corresponding to the second computing element. The example method may also include sending, to the second computing element, a second signal to cause a third computing element to increase heat dissipation from the third computing element to the first computing element.

Abstract: A power glitch signal detection circuit, a security chip and an electronic apparatus are disclosed. The power glitch signal detection circuit includes a voltage sampling module, wherein the voltage sampling module includes: a first metal oxide semiconductor MOS transistor and a capacitor for sampling a power supply voltage, wherein a gate terminal of the first MOS transistor is connected to the capacitor, a source terminal of the first MOS transistor is connected to a ground voltage. The power glitch signal detection circuit further comprises a second MOS transistor and a signal output module. One terminal of the second MOS transistor is connected to a gate terminal of the first MOS transistor, another terminal of the second MOS transistor is connected to the power supply voltage, and a drain terminal of the second MOS transistor is connected to a drain terminal of the first MOS transistor.

Abstract: An information handling system includes a memory module having a first temperature sensor collocated with first memory devices associated with a first memory channel, and a second temperature sensor collocated with second memory devices associated with a second memory channel. A processor receives a first temperature from the first temperature sensor and a second temperature from the second temperature sensor, receives a first power level associated with the first memory channel and a second power level associated with the second memory channel from the memory module, determines a first thermal resistance of the first memory devices based upon the first temperature and the first power level, and determines a second thermal resistance of the second memory device based upon the second temperature and the second power level.

Abstract: A power control apparatus for an in-vehicle camera includes a temperature sensor which measures the temperature in a camera unit; a temperature data acquisition section which acquires periodically measured temperature data; a predicted temperature calculation section which calculates a temperature gradient from the acquired temperature data group and, based on the temperature gradient, calculates a future predicted camera unit temperature; a power supply section which supplies power to an image processing section; a temperature determination section which determines whether predicted temperature is within an operation guarantee temperature of camera unit component parts; and a power supply control section which, based on a determination result, issues a control command to start or stop power supply to the component parts from the power supply section, the power supply being started or stopped with appropriate timing using the predicted temperature, thereby enabling expeditious protection of the component part

Abstract: A processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator.

Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g., to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

Abstract: A device capable of self-detecting and self-allocating additional power and associated method are disclosed. The device includes a first module to route current from first power pins to a voltage rail having the first voltage level. The device includes a second module coupled to second power pins associated with a second voltage level. The second module routes current from the second power pins to the voltage rail having the first voltage level via a connecting voltage rail. The method includes determining, by the device, whether or not a presence of unused power pins is detected. Based on the detection, the method includes calculating a total amount of available additional power, repurposing the unused power pins as actively used power pins, and updating a power budget value based on the total amount of available additional power. The device may dynamically allocate power to accelerators based on a power allocation table and the power budget value.

Abstract: Systems, methods, devices, and computer-implemented instructions for processor power management implemented in a compiler. In some implementations, a characteristic of code is determined. An instruction based on the determined characteristic is inserted into the code. The code and inserted instruction are compiled to generate compiled code. The compiled code is output.

Abstract: An information handling system includes a power supply unit having a power train configured to convert electrical energy received by the power supply unit into electrical energy usable by the information handling system and a microcontroller that includes non-volatile memory holding a line status register. The microcontroller is configured to set or reset the power supply unit for high line only operation, and the information handling system is configured to notify the power supply unit microcontroller to set or reset the power supply unit for high line only operation.