Abstract: A rack in a datacenter is powered by a first power feed and a second power feed. The rack supports a plurality of servers which have a maximum combined power consumption which is greater than a maximum supplied power from either the first power feed or the second power feed. When power is lost from one of the power feeds, a rack manager reduces the total power consumption of the plurality of servers by throttling at least one of the servers and/or shutting off at least one of the plurality of servers.

Abstract: A known randomized data pattern at a predetermined reference voltage of the internal oscilloscope is inputted to an internal oscilloscope of the receiving device for each delay tap element of a plurality of consecutive delay tap elements applied to a system clock of a receiving device. A first delay tap element among the plurality of consecutive delay tap elements in which an output of the internal oscilloscope matches the known randomized data pattern is identified. Responsive to identifying the first delay tap element, a last delay tap element among the plurality of consecutive delay tap elements in which the output of the internal oscilloscope matches the known randomized data pattern is identified.

Abstract: Object Provided is a power supply device and the like capable of improving convenience. Solving means A power supply device according to an embodiment of the present disclosure include a power supply unit that supplies power to an electromedical device, a first impedance control unit disposed on a path of a circulation path of the power between the power supply unit and the electromedical device, excluding an input path for inputting an electrical signal obtained in the electromedical device to another device, and a second impedance control unit disposed on the input path of a path between the power supply unit and the other device. An impedance state of each of the first and second impedance control units transitions in accordance with a supply state of the power to the electromedical device.

Abstract: A memory is provided. The memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips are configured to perform information interaction with the control chip by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges include two consecutive rising edges and/or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle.

Abstract: A data acquisition system and a control method, apparatus, and device therefor, and a medium. The data acquisition system comprises: a signal transmission line, the signal transmission line having multiple first signal delay units connected in series, and the output end of each of the first signal delay units forming an acquisition point; multiple acquisition units, the acquisition units being connected to the acquisition points of the first signal delay units to acquire signals at the acquisition points; a clock unit, configured to generate a control signal; a comparison unit, configured to compare the period of the control signal with the period of a standard signal, and generate an adjustment signal according to the comparison result; and an adjustment unit, configured to adjust a power supply voltage for the signal transmission line and the clock unit according to the adjustment signal, so that the ratio of the period of the control signal to the period of the standard signal meets a set threshold range.

Abstract: Disclosed are a method, an apparatus, and a non-transitory computer-readable storage medium for obtaining applications. The method includes: identifying an external device connected to an interface according to states of pins of the interface; identifying applications which require to use the external device connected to the interface; and displaying at least one of the applications identified.

Abstract: An electronic device comprising a system on chip and an external module. The system on chip includes a plurality of internal subsystems and a power management system including a plurality of internal voltage regulators which supply power to the plurality of internal subsystems. Each of the internal voltage regulators has an associated current limiter. The external module includes at least one external voltage regulator which can provide power to at least one of the internal subsystems. The power management system during a start-up phase enables the internal voltage regulators and the current limiters and in a subsequent phase determines an externally powered set of the internal subsystems, disables the corresponding internal voltage regulators, and disables the current limiters associated with the internal subsystems not externally powered.

Abstract: An example target device is described for facilitating application docking. In various aspects, the target device can comprise a processor. In various instances, the target device can comprise a non-transitory machine-readable memory that can store machine-readable instructions. In various cases, the processor can execute the machine-readable instructions, which can cause the processor to launch, based on a dock request that is to indicate a session of a first instance of an application of an initiator device, a second instance of the application on the target device. In various aspects, the second instance can resume the session. In various instances, the launch can be based on a determination that a dock credential of a Quick Response (QR) code generated by the target device is in the dock request.

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state.

Abstract: Methods and apparatus for performing timed functions in battery-powered, wireless electronic devices, such as sensors or control modules. Such electronic devices comprise a main processor and a co-processor. When the main processor enters a quiescent state in order to preserve battery life, one or more timed functions are transferred from the main processor to the co-processor just before the main processor enters the quiescent state. When the co-processor determines that it is time to perform the timed function, the co-processor wakes the main processor in order for the main processor to perform the timed function.

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Abstract: A system includes a memory device of multiple devices, and a processing device of the multiple devices, coupled with the memory device. The system identifies multiple device temperature values that are each indicative of a temperature at a respective device of the multiple devices of the system. The system determines that at least one device temperature value of the multiple device temperature values satisfies a respective thermal throttling threshold of multiple thermal throttling thresholds. The system performs a power reducing operation to reduce a power consumption of the system in accordance with a power reduction value based on the satisfaction of the respective thermal throttling threshold.

Abstract: The system and method generates a pulse or a signal that is transmitted between a central processing unit or processor and an Ethernet integrated circuit card to program a trigger generator in the IC. The pulse is effectively a 1PPS signal that is provided to the IC, which may be in the form a field programmable gate array to enable timing synchronization. The trigger in the IC may also generates an interrupt to the processor so a driver in the CPU is instructed to set the next trigger. For the trigger to be accurately controlled, the control routine is implemented in the driver existing in kernel space rather than user space. A routine or protocol periodically polls the interrupt to determine when the trigger must be reset.

Abstract: An embodiment for improving a shutdown sequencing of a computer operating system (OS) is provided. The embodiment may include receiving a command to initiate an OS shutdown. The embodiment may also include creating a first list of running tasks to terminate. The embodiment may further include in response to determining there is no historical data, sending a termination request to a particular running task. The embodiment may also include in response to determining the particular running task requires user input to terminate, increasing a weight of the particular running task. The embodiment may further include in response to determining there is an additional particular running task in the created first list, sending the termination request to the additional particular running task. The embodiment may also include in response to determining the additional particular running task requires the user input to terminate, increasing the weight of the additional particular running task.

Abstract: This application discloses a voltage scaling method and an electronic device. The method is applied to an electronic device having a processor and a power supply that supplies power to the processor. The method includes the processor sending power supply scaling information to the power supply based on an operating frequency in a next time period. The method further includes the power supply determining, based on the power supply scaling information, a supply voltage Vout used to supply power to the processor. The supply voltage Vout decreases as a load current of the power supply increases. Vmin?Vout?V, where Vmin is a lowest supply voltage of the processor at the operating frequency in the next time period, and V is a specified supply voltage of the processor at the operating frequency in the next time period.

Abstract: In some examples, an electronic device comprises a battery; a storage device storing a user profile, the user profile comprising a usage pattern of the battery; and a processor coupled to the battery and the storage device, the processor to: receive a battery measurement of the battery and operational data of a first component of the electronic device; calculate a battery consumption of the first component based on the battery measurement; compare the battery consumption to the usage pattern; update, based on the comparison, the user profile using a time series model, wherein inputs to the time series model include the battery measurement and the operational data; and adjust a battery consumption of the electronic device based on the updated user profile.

Abstract: The present disclosure relates to techniques for managing power assertions associated with applications that may run on an electronic device. For example, to reduce power consumption of power available on a power source of the electronic device, the electronic device may start a timer after receiving a request for a power assertion. When the timer expires, the electronic device may enter a low power state.

Abstract: An Internet of Things (IoT) device includes a first memory disposed in a normal zone; a first driver disposed in the normal zone; and a second driver disposed in a secure zone. The first driver is configured to perform: (a) monitoring the first memory to generate data change information of the first memory, the data change information being information on changes of data in the first memory; (b) transmitting the data change information to the second driver; and (c) controlling an operating state of the IoT device based on an instruction for the operating state received from the second driver. The second driver is configured to perform: (d) transmitting the data change information to a specified IoT device management system; and (e) receiving the instruction for the operating state from the IoT device management system and transmitting the instruction for the operating state to the first driver.

Abstract: Dynamic power budget allocation in a multi-processor system is described. In an example, an apparatus includes a plurality of processor units; and a power control component, the power control component to monitor power utilization of each of the plurality of processor units, wherein power consumed by the plurality of processor units is limited by a global power budget. The apparatus is to assign a workload to each of the processor units and is to establish an initial power budget for operation of each of the processor units, and, upon the apparatus determining that one or more processor units require an increased power budget based on one or more criteria, the apparatus is to dynamically reallocate an amount of the global power budget to the one or more processor units.

Abstract: A method of operating a hardware accelerator comprises: implementing a multi-layer neural network using the hardware accelerator; measuring a power consumption of the hardware accelerator while executing a predefined operation on the multi-layer network at a default clock frequency; evaluating one or more power management criteria for the measured power consumption; and, in response to exceeding one of the power management criteria, deciding to reduce the clock frequency relative to the default clock frequency. In the step of measuring a power consumption of the hardware accelerator, per-layer measurements which each relate to fewer than all layers of the neural network may be captured.