Abstract: Systems and methods are provided to perform BIOS recovery for a first information handling system that is in a no-boot state, i.e., in which the original equipment manufacturer (OEM) boot block (OBB) on the first information handling system is corrupted or damaged and thus does not properly execute. OBB BIOS recovery may be achieved using logic executing on a second and different information handling system that is wirelessly communicating with initial boot block (IBB) BIOS firmware that is executing on the first information handling system. The logic executing on the second information handling system may select and download (e.g., from a remote server) a correct uncorrupted and undamaged copy of the BIOS recovery firmware version for the first information handling system, and then wirelessly transfer the downloaded new copy of the OBB BIOS firmware version to the first information handling system via an established secure wireless connection.

Abstract: Bootstrapping a microservices container registry. A computing system node receives an installation package. The receiving computing system node bootstraps an initial invocation of the microservice by first installing a local container registry from the installation package and then by installing the microservice from the installation package. The installation package contains additional components that can be extracted, installed and invoked by executing the microservice at the computing system node after extracting from the local container registry. The installation package is generated by any node of the computing system and contains code corresponding to infrastructure microservices that are installed before invoking microservices that depend on the infrastructure. Temporary domain name services are installed from the installation package at a node-local IP address. The temporary domain name services are switched over to a different domain name service at a different IP address.

Abstract: A circuit device includes: a plurality of circuit blocks, each circuit block being provided with at least one temperature sensor; and a control circuit controlling the plurality of circuit blocks. Each circuit block performs first feedback control for temperature abnormality detection, based on a temperature detection value of the temperature sensor provided in each circuit block. The control circuit performs second feedback control for temperature abnormality detection to each circuit block of the plurality of circuit blocks, based on the temperature detection value of the temperature sensor.

Abstract: The present description concerns an electronic device having an antenna configured to receive a radio frequency signal. The electronic device further includes a control unit. The control unit is off, and the antenna receives a radio frequency signal. The antenna is configured to deliver a first voltage representative of the radio frequency signal to power the control unit with the voltage for the duration of the booting of the control unit.

Abstract: An electronic device is provided. The electronic device includes a processor including a plurality of cores and a memory electrically connected with the processor and storing instructions.

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

Abstract: An application processor and a system on chip (SoC) that incorporates the application processor are provided. The application processor includes a first core configured to process first data per unit time, a second core configured to process second data larger than the first data per unit time, and a lookup table configured to determine whether to activate the first core or the second core based on at least one of an analysis result of a message signal received by a communications processor, a sensing signal supplied to the application processor and a power level supplied to the communications processor.

Abstract: A system comprises a microcontroller system comprising a CPU, an I/O module, and a microcontroller system power input, a power supply comprising a first power supply output providing power at a first power level, and a second power supply output providing power at a second power level, and a switch comprising a signal input communicatively coupled to the I/O module and configured to receive a status signal from the I/O module, a first switch power input electrically coupled to the first power supply output, a second switch power input electrically coupled to the second power supply output, and a switch power output electrically coupled to the microcontroller system power input and configured to output power to the microcontroller system.

Abstract: A BMC-based time management system includes a host system and a baseboard management controller (BMC). The BMC implements a BMC time manager to perform time management and synchronization operations including receiving, from a time source, time information such as a timestamp corresponding to a particular time, e.g., year, month, day, hour, second, and milliseconds, sometimes referred to herein as an initial time. The BMC manager maintains, in accordance with the initial time, a BMC-determined time, referred to herein as the master time. The BMC time manager synchronizes one or more host system time values, also referred to herein as subordinate time values, in accordance with the master time. The one or more subordinate time parameters may include a host OS time, and one or more host device times. In this manner, the BMC maintains the master time and synchronizes host system time values.

Abstract: A system basis chip is described. The system basis chip comprises a power supply circuit configured to receive an input voltage and generate a plurality of voltages, and a control circuit. Specifically, the power supply circuit is configured to selectively switch on a first and a second voltage of the voltages as a function of a control signal. The control circuit measures a resistance value of an external resistor connected to a terminal and selects one of a plurality of configurations as a function of the measured resistance value, wherein a first configuration indicates that said first voltage should be switched on before said second voltage and a second configuration indicates that said second voltage should be switched on before said first voltage. Accordingly, the control circuit may generate the control signal in order to switch on in sequence the first and the second voltage according to the selected configuration.

Abstract: A system and a method for reconstructing an electronic data processing facility is provided. The method includes: accessing information that indicates a predetermined arrangement of hardware components included in the electronic data processing facility; verifying that the hardware components are operational based on the predetermined arrangement; accessing information that indicates a predetermined order of software modules to be installed in the electronic data processing facility; installing the software modules based on the predetermined order; accessing information that indicates a predetermined data set to be stored in a memory of the electronic data processing facility; and verifying that the installed software modules and the stored data set are operational based on a predetermined standard.

Abstract: Disclosed herein are methods and corresponding apparatus and systems for controlling the configuration of a computer system through locking one or more control registers. In some embodiments, a write-enable controller is configured to permit writing to a control register by a software application when the value of a lock bit has been set to indicate that the control register is unlocked. The control register can be locked by setting the lock bit after the control register has been written to, e.g., as part of a system initialization process that places the computer system into a target configuration. After the control register has been locked, the write-enable controller may prevent further writes to the control register, e.g., a write request from the same application that wrote to the control register earlier or a different software application. The locking of the control register can be maintained until system reset.

Abstract: Systems and methods related to a remote configuration system are disclosed. The system includes a processing resource and a non-transitory machine-readable medium storing instructions executable by the processing resource to send an identification code to a server to initiate a system configuration, receive a payload including a configuration instruction responsive to the sent identification code, configure the system utilizing the payload including the configuration instruction, where the system is permanently configured, and store a receipt including the payload responsive to the configuration of the system.

Abstract: Disclosed are various embodiments for a unified boot image that can be used to install an operating system onto a host machine and a respective operating system onto a data processing units (DPU) installed on a host machine. The unified boot image contains installation files for installing an operating system on the host machine and an installation depot that can be used to create a boot image for installing the same or different operating system on the DPU. During installation of an operating system on a host machine, the installation workflow can also require installation of an additional operating system or other configuration of a DPU installed in a host machine. In response to determining that an operating system is to be installed on the DPU, the installation depot can be obtained and reformatted into a downloadable format that is compatible with the DPU.

Abstract: An information handling system includes a basic input/output system (BIOS), multiple graphics processing units (GPUs), and an advanced graphics synchronization node (AGN). The BIOS initiates boot operations for the information handling system. During a pre-extensible firmware interface phase of the boot operations, the BIOS initializes a video memory associated with the GPUs. During the boot operations, the AGN generates a firmware override table based on data in the video memory, and a redirection override table based on the data in the video memory. During operating system runtime operations, the AGN utilizes the firmware override table to synchronize outputs from the GPUs, and utilizes the redirection override table to enable a firmware update for one of the GPUs without a reboot of the information handling system.

Abstract: An electronic apparatus and a hotkey prompt method thereof are provided. The method includes the following steps. A power-on self-test (POST) procedure of a basic input output system (BIOS) is performed. During the POST procedure, a display panel of a keyboard module is controlled to display a first keyboard layout, so as to display at least one hotkey corresponding to at least one hotkey function of the BIOS via the display panel. After a hotkey input operation is received via the keyboard, a first hotkey function of the at least one hotkey function of the BIOS is performed. The hotkey input operation is used to enable the first hotkey function. In response to performing the first hotkey function, the display panel of the keyboard module is controlled to display a second keyboard layout.

Abstract: A computer program product includes a non-volatile computer readable medium and non-transitory program instructions embodied therein, the program instructions being configured to be executable by a processor of a baseboard management controller in a multi-processor system to cause the processor to perform various operations. The operations include initiating disabling of a processor interconnect between first and second central processing units in the multi-processor system and initiating boot of the first central processing unit, wherein the first central processing unit operates in a first partitioned node independent of the second central processing unit.

Abstract: The present disclosure generally relates to dataflow applications. In aspects, a system is disclosed for scheduling execution of feature services within a distributed data flow service (DDFS) framework. Further, the DDFS framework includes a main system-on-chip (SoC), at least one sensing service, and a plurality of feature services. Each of the plurality of feature services include a common pattern with an algorithm for processing the input data, a feature for encapsulating the algorithm into a generic wrapper rendering the algorithm compatible with other algorithms, a feature interface for encapsulating a feature output into a generic interface allowing generic communication with other feature services, and a configuration file including a scheduling policy to execute the feature services. For each of the plurality of feature services, processor(s) schedule the execution of a given feature service using the scheduling policy and execute a given feature service on the standard and/or accelerator cores.

Abstract: A main circuit includes a switching element, and converts electric power input to the main circuit and supplies a result of the conversion to a load. The controller switches a control scheme of the main circuit from a first control scheme to a second control scheme at a first time point when the output value starts to vary and switches the control scheme of the main circuit from the second control scheme to the first control scheme at a second time point when a determination is made that switching of a variation direction of the output value will occur on the basis of a detection value of the detector.

Abstract: Disclosed herein are system, method, and computer program product embodiments for a method of cloud infrastructure optimization. The method identifies an existing infrastructure configuration deployed in a cloud environment and generates a plurality of proposal configurations, each of the plurality of proposal configurations having executable code configured to adjust the existing infrastructure configuration for at least one variable. The method selects a proposal configuration from the plurality of proposal configurations based on the at least one variable adjusted for in the existing infrastructure configuration, and the selected proposal configuration is deployed in the cloud environment. The method then analyzes the selected proposal configuration for a level of adjustment for the at least one variable. The method trains a model engine with existing and new training data.