Patents Examined by Nitin Parekh
  • Patent number: 10388533
    Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: August 20, 2019
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Minrui Yu, Mehul B. Naik
  • Patent number: 10388618
    Abstract: A semiconductor device (10) includes: a substrate (1); a wiring (6) formed above the substrate (1); a titanium nitride film (7) formed on the wiring (6); an oxide film (3) formed on the titanium nitride film (7); a silicon nitride film (4) formed on the oxide film (3); and a pad portion (8) exposing the wiring (6), and formed at a place where a first opening portion (91) formed in the silicon nitride film (4) and a second opening portion (92) formed in the titanium nitride film (7) overlap with each other in plan view, and being inside a third opening portion (93) formed in the oxide film (3) in plan view, wherein the silicon nitride film (4) is formed on top of and in contact with the titanium nitride film (7) inside the third opening portion (93) in plan view.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: August 20, 2019
    Assignee: ABLIC Inc.
    Inventors: Takeshi Morita, Shinjiro Kato, Masaru Akino, Yukihiro Imura
  • Patent number: 10378736
    Abstract: An LED bracket, LED bracket array, LED device and LED display screen are disclosed. The LED bracket includes a PCB circuit substrate and an insulating material. The PCB circuit substrate includes at least two electrically insulated electrode regions. Each electrode region includes a top electrode region, a side electrode region and a bottom electrode region. The side electrode region connects the top electrode region and the bottom electrode region into an integrated structure. The side electrode region is a side surface sunk from outside to an inner part of the PCB circuit substrate. The insulating material is filled in the side electrode region. An upper end surface and a lower end surface of the insulating material do not exceed an upper surface and a lower surface of the PCB circuit substrate. A thickness of the insulating material is less than a thickness of the PCB circuit substrate.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 13, 2019
    Assignee: Foshan NationStar Optoelectronics Co., Ltd.
    Inventors: Chuanbiao Liu, Feng Gu, Yuanbin Lin, Xiangling Luo, Xiaofeng Liu, Xi Zheng, Yan Liu
  • Patent number: 10381285
    Abstract: Provided are a heat dissipation substrate capable of improving heat dissipation properties of an electronic component, and an electric power steering device. In the heat dissipation substrate, a plurality of thermal vias are disposed at least in an electronic component projection region in which a region of a bottom surface portion of the electronic component is projected to a mounting surface in a direction perpendicular to the mounting surface, and a surface density of the thermal vias which occupy the mounting surface per unit area is at least partially different. The plurality of thermal vias are disposed so that the surface density of the thermal vias becomes the greatest in a dense region on an inner side of an edge portion of the electronic component projection region.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: August 13, 2019
    Assignee: NSK LTD.
    Inventor: Shigeru Shimakawa
  • Patent number: 10381319
    Abstract: A core material including a core and a solder plating layer of a (Sn—Bi)-based solder alloy made of Sn and Bi on a surface of the core. Bi in the solder plating layer is distributed in the solder plating layer at a concentration ratio in a predetermined range of, for example, 91.7% to 106.7%. Bi in the solder plating layer is homogeneous, and thus, a Bi concentration ratio is in a predetermined range over the entire solder plating layer including an inner circumference side and an outer circumference side in the solder plating layer.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: August 13, 2019
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Tomoaki Nishino, Shigeki Kondo, Takahiro Hattori, Hiroyoshi Kawasaki, Takahiro Roppongi, Daisuke Soma, Isamu Sato
  • Patent number: 10366947
    Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Reynaldo Corpuz Javier, Alok Kumar Lohia, Andy Quang Tran
  • Patent number: 10366906
    Abstract: The present disclosure provides an electronic package, including a package substrate and an electronic component formed on the package substrate. The substrate includes an insulating portion, a wiring portion embedded in the insulating portion, and a metal board disposed on the insulating portion and in contact with the wiring portion. The metal board is provided with a plurality of electrical contacts and a heat dissipating portion. The metal board can maintain a predefined heat dissipation area via the heat dissipating portion, and be connected to a circuit board via the electrical contacts.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 30, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Hsien-Ming Tsai
  • Patent number: 10361120
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
  • Patent number: 10354934
    Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 16, 2019
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla
  • Patent number: 10347567
    Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Nishikizawa, Yuichi Yato, Hiroi Oka, Tadatoshi Danno, Hiroyuki Nakamura
  • Patent number: 10340245
    Abstract: A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 2, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Jin Seol, Yong Koon Lee
  • Patent number: 10332828
    Abstract: Some embodiments relate to a semiconductor power device that includes a first substrate, a second substrate, a stack and an interconnect structure. The first substrate includes a first patterned electrically conductive layer on a first surface and a switching semiconductor element. The second substrate includes a second surface facing the first surface and a second patterned electrically conductive layer on the second surface. The stack includes an electrically conductive track and a layer of a dielectric material. The layer of the dielectric material is provided on the first or second patterned electrically conductive layer and the layer of the dielectric material isolates the electrically conductive track from the patterned electrically conductive layer on which the stack is provided. The interconnect structure provides at least one electrical connection electrically conductive layers or areas of the substrates.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: June 25, 2019
    Assignees: AGILE POWER SWITCH 3D—INTEGRATION APSI3D, IRT SAINT EXUPERY (AESE)
    Inventors: Jacques Pierre Henri Favre, Jean-Michel Francis Reynes, Raphaël Riva, Bernard José Charles Du Trieu De Terdonck
  • Patent number: 10332818
    Abstract: A component carrier has an interconnected stack with at least one electrically insulating layer structure and/or at least one electrically conductive layer structure, a component embedded in the stack and a diode, and at least one heat removal layer configured for removing heat from the diode and substantially fully covering a whole main surface of the component carrier.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: June 25, 2019
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Mike Morianz, Gerald Weis, Johannes Stahr
  • Patent number: 10332861
    Abstract: The present disclosure provides a method for interconnecting components. First and second substrates are provided. First and second components are respectively provided on the first and second substrates, in which the second component is not in contact with the first component. Then, a joint component is formed between the first and second components by passing a flow of a fluid comprising ions of a conductive material between the first and second components and electrolessly plating the first and second components by the conductive material so that the joint component is electrically connected between the first and second components. The present disclosure also provides related interconnection structures and a fixture for forming a related microchannel structure.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 25, 2019
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Cheng-Heng Kao, Han-Tang Hung, Chun-Hsiang Yang, Yan-Bin Chen
  • Patent number: 10325863
    Abstract: According to one embodiment, a semiconductor device includes an insulating film. The insulating film includes a first insulating particle, and a second insulating particle. A particle size of at least one of the first insulating particle or the second insulating particle exceeds 0 nm and being not more than 30 nm. An average size of a void between the first insulating particle and the second insulating particle exceeds 0 nm and being not more than 10 nm.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 18, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masakuni Ikagawa
  • Patent number: 10319696
    Abstract: Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Patent number: 10319663
    Abstract: A semiconductor memory device includes a housing having a wall, a circuit board located in the housing and spaced from the wall and extending along the surface of the wall, a memory located on the circuit board, a heat conduction member interposed, and compressed, between the wall and the memory. The wall includes an uneven region comprising contact portions contacting the heat conduction member and recess portions located between the contact portions. The recess portions are recessed inwardly of the wall from the ends of the contact portions in a direction away from the location of the memory.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 11, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenichi Sawanaka
  • Patent number: 10297562
    Abstract: Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: May 21, 2019
    Assignee: ABLIC INC.
    Inventors: Kaku Igarashi, Shinjiro Kato, Hisashi Hasegawa, Masaru Akino, Yukihiro Imura
  • Patent number: 10297566
    Abstract: A semiconductor structure includes a substrate, a chip, a plurality of conductive bumps, a flexible printed circuit (FPC) board and a plurality of circuit patterns. The chip is disposed on the substrate and includes a plurality of pads. The conductive bumps are disposed on the pads respectively. The FPC board is connected between the substrate and the chip, and the conductive bumps penetrate through an end of the FPC board. The circuit patterns are disposed on the FPC board and electrically connected to the conductive bumps and the substrate.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: May 21, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Yu-Ming Chen
  • Patent number: 10283535
    Abstract: A method for producing a display device includes locating a substrate, including a plurality of pixels, on a jig including a magnet; locating a plate formed of a magnetic material on the substrate to secure the substrate; and folding back an end portion of the substrate in a state where the substrate is held between the jig and the plate.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 7, 2019
    Assignee: Japan Display Inc.
    Inventor: Takashi Saeki