Patents Examined by Nitin Parekh
  • Patent number: 11456278
    Abstract: Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Patent number: 11450606
    Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 20, 2022
    Assignee: MediaTek Inc.
    Inventors: Yen-Yao Chi, Nai-Wei Liu, Tzu-Hung Lin, Ta-Jen Yu, Wen-Sung Hsu
  • Patent number: 11450639
    Abstract: A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad with a first bonding surface positioned away from the stack structure, and a second bonding pad; a carrier comprising a connecting surface; a third bonding pad which comprises a second bonding surface and is arranged on the connecting surface, and a fourth bonding pad arranged on the connecting surface of the carrier; and a conductive connecting layer comprising a first conductive part, comprising a first outer contour, and formed between and directly contacting the first bonding pad and the third bonding pad; a second conductive part formed between the second bonding pad and the fourth bonding pad; and a blocking part covering the first conductive part to form a covering area, wherein the first bonding surface comprises a first position which is the closest to the carrier within the covering area and a second position which is the farthest from the carrier within the covering area in a cross section vie
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: September 20, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-An Liao, Shau-Yi Chen, Ming-Chi Hsu, Chun-Hung Liu, Min-Hsun Hsieh
  • Patent number: 11450614
    Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Joo Kim, Sun Chul Kim, Min Keun Kwak, Hyun Ki Kim, Hyung Gil Baek, Yong Kwan Lee
  • Patent number: 11444004
    Abstract: A cooler of the present invention is provided with a case having a top plate, a bottom plate, and a side plate, cooling fins disposed inside the case, and a flow path for cooling fluid that comes into contact with the cooling fins and that flows through the interior of the case, the cooler cooling an object to be cooled in contact with the top plate or the bottom plate. The cooling fins have a shaft part and vane parts that protrude outward from the shaft part and extend spirally in the axial direction; the overall cooling fin configuration constituting a quadrangular column shape. The cooling fins are disposed in contact with at least the top plate and the bottom plate, and the flow path has a spiral-formed configuration formed by the vane parts, the top plate, and the bottom plate.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: September 13, 2022
    Assignees: FUJI ELECTRIC CO., LTD., WASEDA UNIVERSITY
    Inventors: Ryoichi Kato, Yoshinari Ikeda, Hiromichi Gohara, Tomoyuki Miyashita, Shingo Otake
  • Patent number: 11437707
    Abstract: The present disclosure provides an antenna package structure and packaging method. The package structure includes: a metal joint pin fabricated by using a wire bonding process; and a packaging layer, covering the metal joint pin. An antenna circuit chip and an antenna metal layer are electrically connected to two ends of the antenna feeder package structure.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: September 6, 2022
    Assignee: SJ SEMICONDUCTOR(JIANGYIN) CORPORATION
    Inventors: Jangshen Lin, Yenheng Chen, Chengchung Lin, Chengtar Wu
  • Patent number: 11437307
    Abstract: A device that includes a first die and a package substrate. The package substrate includes a dielectric layer, a plurality of vias formed in the dielectric layer, a first plurality of interconnects formed on a first metal layer of the package substrate, and a second plurality of interconnects formed on a second metal layer of the package substrate. The device includes a first series of first solder interconnects arranged in a first direction, the first series of first solder interconnects configured to provide a first electrical connection; a second series of first solder interconnects arranged in the first direction, the second series of first solder interconnects configured to provide a second electrical connection; a first series of second solder interconnects arranged in a second direction, the first series of second solder interconnects configured to provide the first electrical connection.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: September 6, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Abdolreza Langari, Yuan Li, Shrestha Ganguly, Terence Cheung, Ching-Liou Huang, Hui Wang
  • Patent number: 11410968
    Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Shang-Yun Hou
  • Patent number: 11410934
    Abstract: A substrate, a semiconductor package device and a method of manufacturing a semiconductor device package are provided. The substrate includes a low density wiring structure, a first middle density wiring structure and high density wiring structure. The first middle density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure is electrically connected to the low density wiring structure. The high density wiring structure and the first middle density wiring structure are disposed side by side. A line space of a circuit layer of the low density wiring structure is greater than a line space of a circuit layer of the first middle density wiring structure. The line space of the circuit layer of the first middle density wiring structure is greater than a line space of a circuit layer of the high density wiring structure.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 9, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ian Hu, Shin-Luh Tarng
  • Patent number: 11393774
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 19, 2022
    Assignee: STMicroelectronics, Inc.
    Inventor: Ian Harvey Arellano
  • Patent number: 11380633
    Abstract: A radio frequency module includes a radio frequency integrated circuit (RFIC) to input or output a base signal and a radio frequency (RF) signal having a higher frequency than the base signal, a wiring via extending upward from the RFIC and a feed line electrically connected to the wiring via to provide a transmission path of the RF signal, a second ground layer surrounding the feed line, a first ground layer spaced above the second ground layer, a third ground layer between the second ground layer and the RFIC, a feed-line insulating layer disposed between the first and third ground layers, an IC wiring layer between the third ground layer and the RFIC, electrically connected to the RFIC, and providing a transmission path of the base signal, and an IC insulating layer between the third ground layer and the RFIC, having a higher dielectric constant than the feed-line insulating layer.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: July 5, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myeong Woo Han, Young Sik Hur, Won Gi Kim, Soo Ki Choi
  • Patent number: 11355419
    Abstract: The present invention relates to a power semiconductor module including a first heat dissipation substrate, a semiconductor chip, a lead plate, a PCB, and a heat dissipation plate that are packaged within a casing, wherein dualization of a heat dissipation structure is applied to facilitate superior heat dissipation performance compared to a conventional power semiconductor module.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: June 7, 2022
    Assignee: Amosense Co., Ltd.
    Inventor: Ik-Seong Park
  • Patent number: 11348854
    Abstract: A semiconductor package structure includes a package substrate, an encapsulant, at least one passage and at least one semiconductor element. The encapsulant is disposed on the package substrate and has a peripheral surface, and includes a first encapsulant portion and a second encapsulant portion spaced apart from the first encapsulant portion. The at least one passage is defined by the first encapsulant portion and the second encapsulant portion, and the passage has at least one opening in the peripheral surface of the encapsulant. The at least one semiconductor element is disposed on the package substrate and exposed in the passage.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: May 31, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: I-Chia Lu, Mao-Sung Hsu
  • Patent number: 11342275
    Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: May 24, 2022
    Assignee: NXP USA, Inc.
    Inventors: Yun Wei, Fernando A. Santos, Lakshminarayan Viswanathan, Scott Duncan Marshall
  • Patent number: 11328971
    Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
  • Patent number: 11322423
    Abstract: An electronic control device includes: a board; a heat generating component mounted on the board; a heat conductive sheet thermally coupled to one surface of the heat generating component located on a side opposite to the board side; and a cooling mechanism thermally coupled to the heat conductive sheet. The heat conductive sheet includes a folded structure having a plurality of folded-back portions and a plurality of connection portions provided between the folded-back portions, and the plurality of folded-back portions of the heat conductive sheet is thermally coupled to each of the heat generating component and the cooling mechanism.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: May 3, 2022
    Assignee: Hitachi Astemo, Ltd.
    Inventors: Shinya Kawakita, Hideyuki Sakamoto
  • Patent number: 11315854
    Abstract: A semiconductor device, including a conductive plate having a front surface that includes a plurality of bonding regions and a plurality of non-bonding regions in peripheries of the bonding regions, a plurality of semiconductor elements mounted on the conductive plate in the bonding regions, and a resin encapsulating therein at least the plurality of semiconductor elements and the front surface of the conductive plate. The conductive plate has, at the front surface thereof in the non-bonding regions, a plurality of holes.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: April 26, 2022
    Assignees: FUJI ELECTRIC CO., LTD., FURUKAWA ELECTRIC CO., LTD.
    Inventors: Ryoichi Kato, Hiromichi Gohara, Yoshinari Ikeda, Yoshikazu Takahashi, Kuniteru Mihara, Isao Takahashi
  • Patent number: 11315846
    Abstract: An object of the present invention is to provide a semiconductor device in which peeling between a mold resin and a substrate is suppressed. A semiconductor device 1 includes a semiconductor chip 20 and a substrate 10 that are molded with a mold resin layer 40. The semiconductor device 1 includes a resin layer 50 having a thickness of 200 nm or less different from the mold resin layer 40 between the cured mold resin layer 40 and the substrate 10. The resin layer 50 present between the mold resin layer 40 and the substrate 10 is preferably present on a periphery of 30% or more of the chip when an entire peripheral length of the chip is 100%.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: April 26, 2022
    Assignee: NAMICS CORPORATION
    Inventors: Hiroki Myodo, Toyokazu Hotchi, Masaaki Hoshiyama
  • Patent number: 11315857
    Abstract: A package structure is provided. The package structure includes a leadframe including a first portion and a second portion. The first portion includes a first base part and a plurality of first extended parts connected to the first base part. The second portion includes a second base part and a plurality of second extended parts connected to the second base part. The first extended parts and the second extended parts are arranged in such a way that they alternate with each other. In the package structure, a chip is disposed on a part of the first extended parts of the first portion and the second extended parts of the second portion of the leadframe. The package structure further includes a plurality of protrusions, opposite to the chip, disposed on the first extended parts and the second extended parts.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: April 26, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Peng-Hsin Lee
  • Patent number: 11315843
    Abstract: Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 26, 2022
    Assignee: Intel Corporation
    Inventors: Yi Elyn Xu, Bilal Khalaf, Dennis Sean Carr