Abstract: A semiconductor device comprising a DC-DC converter including a primary-side circuit and a secondary-side circuit including a first semiconductor package accommodating a first semiconductor element group including a first semiconductor element and a second semiconductor element. The first semiconductor element and the second semiconductor element are stacked. The first semiconductor element group is a MOSFET, an IGBT, or a diode.

Abstract: A semiconductor package comprises a first redistribution substrate including first interconnection layers sequentially stacked on each other, a semiconductor chip mounted on the first redistribution substrate, a mold layer disposed on the first redistribution substrate and surrounding the semiconductor chip, a second redistribution substrate disposed on the mold layer and including second interconnection layers sequentially stacked on each other, a connection terminal disposed beside the semiconductor chip to connect the first and second redistribution substrates to each other, and outer terminals disposed on a bottom surface of the first redistribution substrate. Each of the first and second interconnection layers may include an insulating layer and a wire pattern in the insulating layer. The first redistribution substrate may have substantially the same thickness as the second redistribution substrate, and the first interconnection layers may be thinner than the second interconnection layers.

Abstract: A semiconductor package includes a semiconductor chip on a first redistribution substrate, a molding layer that covers the semiconductor chip, and a second redistribution substrate on the molding layer and that includes a dielectric layer, a redistribution pattern, and a conductive pad. The dielectric layer includes a lower opening that exposes the conductive pad, and an upper opening connected to the lower opening and that is wider than the lower opening. The semiconductor package also comprises a redistribution pad on the conductive pad and that covers a sidewall of the lower opening and a bottom surface of the upper opening. A top surface of the dielectric layer is located at a higher level than a top surface of the redistribution pad. The top surface of the redistribution pad is located on the bottom surface of the upper opening.

Abstract: An electronic device includes a circuit board, a lower IC package in which a lower IC chip is sealed on a lower package substrate by a lower resin portion being mounted on the substrate via a lower solder connection portion, and an upper IC package in which an upper IC chip is sealed on an upper package substrate by an upper resin portion being mounted on the lower IC package via an upper solder connection portion. The upper IC package is provided with a rigid body having a smaller linear expansion coefficient in a plane direction than that of the upper resin portion. The rigid body is arranged directly above a boundary between the lower IC chip and the lower resin portion.

Abstract: A semiconductor structure includes a substrate component, an IC die component over the substrate component, and a composite redistribution structure interposed between and electrically coupled to the substrate and IC die components. The composite redistribution structure includes a local interconnect component between a first redistribution structure overlying the substrate component and a second redistribution structure underlying the IC die component, and an insulating encapsulation between the first and second redistribution structures and embedding the local interconnect component therein.

Abstract: A method includes bonding a top die to a bottom die, depositing a first dielectric liner on the top die, and depositing a gap-fill layer on the first dielectric liner. The gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon oxide. The method further includes etching the gap-fill layer and the first dielectric liner to form a through-opening, wherein a metal pad in the bottom die is exposed to the through-opening, depositing a second dielectric liner lining the through-opening, filling the through-opening with a conductive material to form a through-via connecting to the metal pad, and forming a redistribution structure over and electrically connecting to the top die and the through-via.

Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

Abstract: A Cu interconnect and a method of forming a Cu interconnect of damascene process is provided. A barrier layer is formed at a sidewall and a bottom of a through hole and a groove, constructing a Cu interconnecting line. The barrier layer comprises a metal crystal adhesion layer or a graphene layer. The metal crystal adhesion layer may be a Co, Ru or Os crystal layer. The metal crystal adhesion layer may enhance adhesion of Cu, inhibit diffusion of Cu toward a dielectric layer efficiently, and promoting electro-migration of Cu. The graphene layer may be an Carbon allotrope/graphene complex layer. The graphene layer may provide lower resistance for the Cu interconnect and increase adhesion between barrier and dielectric layer to improve EM. Both the metal crystal adhesion layer and the graphene layer may efficiently reduce the total thickness of the barrier layer and the first barrier layer to efficiently decrease resistance of the through hole.

Abstract: Provided are a semiconductor device and an inverter device with a decrease in yield being suppressed by preventing the adhesive from leaking into the inside of the semiconductor device. A heat sink, a wiring board provided on the heat sink, a semiconductor chip provided on the wiring board, a case housing provided on the heat sink so as to surround the wiring board and the semiconductor chip, an adhesive that adheres a lower surface joint portion of the case housing and an upper surface joint portion of the heat sink, a sealing material that fills the case housing and covers the wiring board and the semiconductor chip, and a convex portion provided on the lower surface joint portion of the case housing or the upper surface joint portion of the heat sink, that separates the adhesive from the sealing material are included.

Abstract: Methods and structures for manufacturing one or more System in a Package (SiP) devices, where the functionality of a packaged SiP device may be modified by additional components.

Abstract: A semiconductor package includes a base substrate having a plurality of upper pads and a plurality of first and second lower pads, a semiconductor chip disposed on the base substrate and electrically connected to the plurality of upper pads, a solder resist layer having a plurality of openings exposing a region of each of the plurality of first and second lower pads, the exposed regions of the plurality of first and second lower pads having the same size, a plurality of first external connection conductors respectively disposed on the exposed regions of the plurality of first lower pads and having a first height and a first volume, and a plurality of second external connection conductors respectively disposed on the exposed regions of the plurality of second lower pads and having a second height, greater than the first height, and a second volume, greater than the first volume.

Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.

Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

Abstract: A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. The first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. The second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.

Abstract: A semiconductor package includes a circuit structure, a first redistribution layer, a second redistribution layer, a first encapsulant, a bus die and a plurality of through vias. The first redistribution layer is disposed over the circuit structure. The second redistribution layer is disposed over the first redistribution layer. The first encapsulant is disposed between the first redistribution layer and the second redistribution layer. The through vias surround the bus die. The first encapsulant is extended along an entire sidewall of the bus die, and a first surface of the bus die is substantially coplanar with top surfaces of the first encapsulant and the plurality of through vias.

Abstract: A semiconductor device includes an insulating layer, conductors, a semiconductor element and a sealing resin. The insulating layer has first and second surfaces opposite to each other in the thickness direction. Each conductor has an embedded part whose portion is embedded in the insulating layer and a redistribution part disposed at the second surface and connected to the embedded part. The semiconductor element has electrodes provided near the first surface and connected the embedded parts of the conductors. The semiconductor element is in contact with the first surface. The sealing resin partially covers the semiconductor element and is in contact with the first surface. The redistribution parts include portions outside the semiconductor element as viewed in the thickness direction. The insulating layer has grooves recessed from the second surface in the thickness direction. The redistribution parts are in contact with the grooves.

Abstract: This application provides an embedded packaging structure, a preparation method thereof, and a terminal device. The embedded packaging structure includes a substrate frame, and a first through hole and a second through hole that run through the substrate frame in a thickness direction of the substrate frame. A metal connection electrode is disposed in the first through hole, an electronic component is embedded in the second through hole, and a pin of the electronic component is exposed at a hole opening of the second through hole. The substrate frame is made of silicon or a ceramic. Compared with a prior art substrate frame formed by using a resin material, the substrate frame in this application has better heat dissipation performance, moisture resistance, and strength in addition to providing insulation.

Abstract: In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.

Abstract: A method of processing a wafer to divide the wafer into individual device chips, includes a second modified layer forming step of applying a laser beam to the wafer while positioning a focused spot of the laser beam inside the wafer along the projected dicing lines extending in a second direction intersecting with a first direction, thereby forming second modified layers in the wafer along the projected dicing lines extending in the second direction. In the second modified layer forming step, when the focused spot of the laser beam along the projected dicing lines extending in the second direction reaches first modified layers, the focused spot of the laser beam is shifted along the first modified layers to thereby undulate the laser beam in a staggered pattern to prevent the second modified layers from being formed straight in the wafer along the projected dicing lines extending in the second direction.

Abstract: Disclosed is a semiconductor package comprising a first redistribution substrate; a solder ball on a bottom surface of the first redistribution substrate; a second redistribution substrate; a semiconductor chip between a top surface of the first redistribution substrate and a bottom surface of the second redistribution substrate; a conductive structure electrically connecting the first redistribution substrate and the second redistribution substrate, the conductive structure laterally spaced apart from the semiconductor chip and including a first conductive structure and a second conductive structure in direct contact with a top surface of the first conductive structure; and a conductive seed pattern between the first redistribution substrate and the first conductive structure. A material of first conductive structure and a material of the second conductive structure may be different from a material of the solder ball.