Patents Examined by Nitin Parekh
  • Patent number: 12293972
    Abstract: A semiconductor device has a leadframe and a first electrical component including a first surface disposed on the leadframe. A first clip bond is disposed over a second surface of the first electrical component. The first clip bond extends vertically through the semiconductor device. The first clip bond has a vertical member, horizontal member connected to the vertical member, die contact integrated with the horizontal member, and clip foot extending from the vertical member. A second electrical component has a first surface disposed on the first clip bond. A second clip bond is disposed over a second surface of the second electrical component opposite the first surface of the second electrical component. An encapsulant is deposited around the first electrical component and first clip bond. A second electrical component is disposed over the encapsulant. The clip foot is exposed from the encapsulant.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: May 6, 2025
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Natawat Kasikornrungroj, Phongsak Sawasdee, Wannasat Panphrom
  • Patent number: 12288770
    Abstract: Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: April 29, 2025
    Assignee: NXP B.V.
    Inventors: Kuan-Hsiang Mao, Norazham Mohd Sukemi, Chin Teck Siong, Tsung Nan Lo, Wen Hung Huang
  • Patent number: 12283556
    Abstract: A package structure is provided. The package structure includes a die, an encapsulant and a RDL structure. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die. The redistribution layer includes a first seed layer and a first conductive layer surrounded by the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.
    Type: Grant
    Filed: January 23, 2024
    Date of Patent: April 22, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee
  • Patent number: 12278171
    Abstract: A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: April 15, 2025
    Assignee: Infineon Technologies AG
    Inventors: Chan Lam Cha, Wern Ken Daryl Wee, Hoe Jian Chong, Chin Kee Leow
  • Patent number: 12272627
    Abstract: A semiconductor device comprising a DC-DC converter including a primary-side circuit and a secondary-side circuit including a first semiconductor package accommodating a first semiconductor element group including a first semiconductor element and a second semiconductor element. The first semiconductor element and the second semiconductor element are stacked. The first semiconductor element group is a MOSFET, an IGBT, or a diode.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: April 8, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hiroshi Yamamoto
  • Patent number: 12261103
    Abstract: A semiconductor package includes a semiconductor chip on a first redistribution substrate, a molding layer that covers the semiconductor chip, and a second redistribution substrate on the molding layer and that includes a dielectric layer, a redistribution pattern, and a conductive pad. The dielectric layer includes a lower opening that exposes the conductive pad, and an upper opening connected to the lower opening and that is wider than the lower opening. The semiconductor package also comprises a redistribution pad on the conductive pad and that covers a sidewall of the lower opening and a bottom surface of the upper opening. A top surface of the dielectric layer is located at a higher level than a top surface of the redistribution pad. The top surface of the redistribution pad is located on the bottom surface of the upper opening.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: March 25, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yonghwan Kwon
  • Patent number: 12261106
    Abstract: A semiconductor package comprises a first redistribution substrate including first interconnection layers sequentially stacked on each other, a semiconductor chip mounted on the first redistribution substrate, a mold layer disposed on the first redistribution substrate and surrounding the semiconductor chip, a second redistribution substrate disposed on the mold layer and including second interconnection layers sequentially stacked on each other, a connection terminal disposed beside the semiconductor chip to connect the first and second redistribution substrates to each other, and outer terminals disposed on a bottom surface of the first redistribution substrate. Each of the first and second interconnection layers may include an insulating layer and a wire pattern in the insulating layer. The first redistribution substrate may have substantially the same thickness as the second redistribution substrate, and the first interconnection layers may be thinner than the second interconnection layers.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 25, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeonjeong Hwang, Kyoung Lim Suk, Seokhyun Lee, Jaegwon Jang
  • Patent number: 12261156
    Abstract: An electronic device includes a circuit board, a lower IC package in which a lower IC chip is sealed on a lower package substrate by a lower resin portion being mounted on the substrate via a lower solder connection portion, and an upper IC package in which an upper IC chip is sealed on an upper package substrate by an upper resin portion being mounted on the lower IC package via an upper solder connection portion. The upper IC package is provided with a rigid body having a smaller linear expansion coefficient in a plane direction than that of the upper resin portion. The rigid body is arranged directly above a boundary between the lower IC chip and the lower resin portion.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: March 25, 2025
    Assignee: DENSO CORPORATION
    Inventor: Hiroyoshi Kunieda
  • Patent number: 12249566
    Abstract: A method includes bonding a top die to a bottom die, depositing a first dielectric liner on the top die, and depositing a gap-fill layer on the first dielectric liner. The gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon oxide. The method further includes etching the gap-fill layer and the first dielectric liner to form a through-opening, wherein a metal pad in the bottom die is exposed to the through-opening, depositing a second dielectric liner lining the through-opening, filling the through-opening with a conductive material to form a through-via connecting to the metal pad, and forming a redistribution structure over and electrically connecting to the top die and the through-via.
    Type: Grant
    Filed: November 21, 2023
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Jung Wu, Ken-Yu Chang, Hao-Wen Ko, Tsang-Jiuh Wu
  • Patent number: 12249587
    Abstract: A semiconductor structure includes a substrate component, an IC die component over the substrate component, and a composite redistribution structure interposed between and electrically coupled to the substrate and IC die components. The composite redistribution structure includes a local interconnect component between a first redistribution structure overlying the substrate component and a second redistribution structure underlying the IC die component, and an insulating encapsulation between the first and second redistribution structures and embedding the local interconnect component therein.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: March 11, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chen-Hua Yu, Yu-Min Liang, Jung-Wei Cheng
  • Patent number: 12243773
    Abstract: A Cu interconnect and a method of forming a Cu interconnect of damascene process is provided. A barrier layer is formed at a sidewall and a bottom of a through hole and a groove, constructing a Cu interconnecting line. The barrier layer comprises a metal crystal adhesion layer or a graphene layer. The metal crystal adhesion layer may be a Co, Ru or Os crystal layer. The metal crystal adhesion layer may enhance adhesion of Cu, inhibit diffusion of Cu toward a dielectric layer efficiently, and promoting electro-migration of Cu. The graphene layer may be an Carbon allotrope/graphene complex layer. The graphene layer may provide lower resistance for the Cu interconnect and increase adhesion between barrier and dielectric layer to improve EM. Both the metal crystal adhesion layer and the graphene layer may efficiently reduce the total thickness of the barrier layer and the first barrier layer to efficiently decrease resistance of the through hole.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: March 4, 2025
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Zhaosheng Meng, Zhuangzhuang Wu, Min-Hwa Chi
  • Patent number: 12243790
    Abstract: Provided are a semiconductor device and an inverter device with a decrease in yield being suppressed by preventing the adhesive from leaking into the inside of the semiconductor device. A heat sink, a wiring board provided on the heat sink, a semiconductor chip provided on the wiring board, a case housing provided on the heat sink so as to surround the wiring board and the semiconductor chip, an adhesive that adheres a lower surface joint portion of the case housing and an upper surface joint portion of the heat sink, a sealing material that fills the case housing and covers the wiring board and the semiconductor chip, and a convex portion provided on the lower surface joint portion of the case housing or the upper surface joint portion of the heat sink, that separates the adhesive from the sealing material are included.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: March 4, 2025
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Miyagi, Hideki Tsukamoto, Takuro Mori, Masaru Furukawa, Korehide Okamoto, Takamasa Oda, Seiji Saiki, Takeshi Ogawa
  • Patent number: 12243794
    Abstract: Methods and structures for manufacturing one or more System in a Package (SiP) devices, where the functionality of a packaged SiP device may be modified by additional components.
    Type: Grant
    Filed: November 24, 2023
    Date of Patent: March 4, 2025
    Assignee: OCTAVO SYSTEMS LLC
    Inventors: Michael Kenneth Conti, Christopher Lloyd Reinert, Masood Murtuza
  • Patent number: 12243824
    Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu
  • Patent number: 12230557
    Abstract: A semiconductor package includes a base substrate having a plurality of upper pads and a plurality of first and second lower pads, a semiconductor chip disposed on the base substrate and electrically connected to the plurality of upper pads, a solder resist layer having a plurality of openings exposing a region of each of the plurality of first and second lower pads, the exposed regions of the plurality of first and second lower pads having the same size, a plurality of first external connection conductors respectively disposed on the exposed regions of the plurality of first lower pads and having a first height and a first volume, and a plurality of second external connection conductors respectively disposed on the exposed regions of the plurality of second lower pads and having a second height, greater than the first height, and a second volume, greater than the first volume.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: February 18, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sangwon Lee
  • Patent number: 12224251
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Grant
    Filed: December 6, 2023
    Date of Patent: February 11, 2025
    Assignee: STMicroelectronics, Inc.
    Inventor: Ian Harvey Arellano
  • Patent number: 12218020
    Abstract: A semiconductor package includes a circuit structure, a first redistribution layer, a second redistribution layer, a first encapsulant, a bus die and a plurality of through vias. The first redistribution layer is disposed over the circuit structure. The second redistribution layer is disposed over the first redistribution layer. The first encapsulant is disposed between the first redistribution layer and the second redistribution layer. The through vias surround the bus die. The first encapsulant is extended along an entire sidewall of the bus die, and a first surface of the bus die is substantially coplanar with top surfaces of the first encapsulant and the plurality of through vias.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yi Wu, Chen-Hua Yu, Chung-Shi Liu, Yu-Min Liang
  • Patent number: 12218001
    Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
  • Patent number: 12218044
    Abstract: A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. The first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. The second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: February 4, 2025
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Nobuhiro Kinoshita, Shuuichi Kariyazaki, Keita Tsuchiya
  • Patent number: 12211817
    Abstract: A semiconductor device includes an insulating layer, conductors, a semiconductor element and a sealing resin. The insulating layer has first and second surfaces opposite to each other in the thickness direction. Each conductor has an embedded part whose portion is embedded in the insulating layer and a redistribution part disposed at the second surface and connected to the embedded part. The semiconductor element has electrodes provided near the first surface and connected the embedded parts of the conductors. The semiconductor element is in contact with the first surface. The sealing resin partially covers the semiconductor element and is in contact with the first surface. The redistribution parts include portions outside the semiconductor element as viewed in the thickness direction. The insulating layer has grooves recessed from the second surface in the thickness direction. The redistribution parts are in contact with the grooves.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: January 28, 2025
    Assignee: ROHM CO., LTD.
    Inventor: Kazunori Fuji