Patents Examined by Nitin Parekh
  • Patent number: 10923435
    Abstract: A semiconductor package includes a substrate having at least one semiconductor chip on a top surface of the substrate; a ground ring, on the top surface of the substrate, surrounding the at least one semiconductor chip; a metal-post reinforced glue wall disposed on the ground ring, surrounding the at least one semiconductor chip; a molding compound surrounding the at least one semiconductor chip, wherein a rear surface of the at least one semiconductor chip is flush with an upper surface of the molding compound; a conductive layer disposed on the molding compound and in direct contact with the rear surface of the semiconductor chip and the metal-post reinforced glue wall; a solder layer disposed on the conductive layer; and a heat sink disposed on the solder layer.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: February 16, 2021
    Inventors: Shiann-Tsong Tsai, Hsien-Chou Tsai, Hsien-Wei Tsai, Yen-Mei Tsai Huang
  • Patent number: 10910335
    Abstract: A light-emitting module includes a common carrier; a plurality of semiconductor devices formed on the common carrier, and each of the plurality of semiconductor devices including three semiconductor dies; a carrier including a connecting surface; a third bonding pad and a fourth bonding pad formed on the connecting surface; and a connecting layer. One of the three semiconductor dies includes a stacking structure; a first bonding pad; and a second bonding pad with a shortest distance less than 150 microns between the first bonding pad. The connecting layer includes a first conductive part including a first conductive material having a first shape; and a blocking part covering the first conductive part and including a second conductive material having a second shape with a diameter in a cross-sectional view. The first shape has a height greater than the diameter.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 2, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-An Liao, Shau-Yi Chen, Ming-Chi Hsu, Chun-Hung Liu, Min-Hsun Hsieh
  • Patent number: 10886594
    Abstract: The present disclosure provides a packaging structure and a packaging method for an antenna. The packaging structure comprises a redistribution layer, having a first surface and an opposite second surface; a first metal joint pin, formed on the second surface of the redistribution layer; a first packaging layer, disposed on the redistribution layer covering the first metal joint pin; a first antenna metal layer, patterned on the first packaging layer, and a portion of the first antenna metal layer electrically connects with the first metal joint pin; a second metal joint pin, formed on the first antenna metal layer; a second packaging layer, disposed on the first antenna metal layer covering the second metal joint pin; a second antenna metal layer, formed on the second packaging layer; and a metal bump and an antenna circuit chip, bonded to the first surface of the redistribution layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 5, 2021
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin
  • Patent number: 10886232
    Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: January 5, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park, Giorgio Cellere, Diego Tonini, Vincent DiCaprio, Kyuil Cho
  • Patent number: 10879147
    Abstract: A method of manufacturing a package structure includes the following processes. A carrier is provided. An adhesive layer is formed on the carrier. A die is attached to the carrier through the adhesive layer. An encapsulant is formed over the carrier to laterally encapsulate the die. A polymer material is formed over the carrier along a surface of the adhesive layer, a surface of the encapsulant and a top surface of the die. A first portion of the polymer material directly on an edge of the carrier has a first thickness larger than a second thickness of a second portion of the polymer material directly on the top surface of the die. A redistribution layer is formed to penetrate through the second portion of the polymer layer and electrically connect to the die.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
  • Patent number: 10879183
    Abstract: A device includes a redistribution structure, a semiconductor device on the redistribution structure, a top package over the semiconductor device, the top package including a second semiconductor device, a molding compound interposed between the redistribution structure and the top package, a set of through vias between and electrically connecting the top package to the redistribution structure, and an interconnect structure disposed within the molding compound and electrically connecting the top package to the redistribution structure, the interconnect structure including a substrate and a passive device formed in the substrate, wherein the interconnect structure is free of active devices.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu
  • Patent number: 10879145
    Abstract: An electronic device includes electronic components, a molded resin element wherein the electronic components are embedded and secured, and a heat transfer layer; the heat transfer layer has a higher thermal conductivity than the molded resin element. The heat transfer layer is in contact with portions of the electronic components other than an electrode pad and a terminal. This prevents increases in the cost of manufacturing the electronic device and the allows the electronic device to be thinner.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: December 29, 2020
    Assignee: OMRON Corporation
    Inventor: Wakahiro Kawai
  • Patent number: 10867963
    Abstract: A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Chien-Ming Chiu, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10861827
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Patent number: 10854951
    Abstract: The present disclosure provides an antenna package structure and an antenna packaging method for a semiconductor chip. The package structure includes an antenna circuit chip, a first rewiring layer, an antenna structure, a second metal connecting column, a second packaging layer, a second antenna metal layer, and a second metal bump. The antenna circuit chip, the antenna structure, and the second antenna metal layer are interconnected by using two rewiring layers and two layers of metal connecting columns.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 1, 2020
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin
  • Patent number: 10847693
    Abstract: A light emitting device includes a resin package having a rectangular shape in a top view and two short-side lateral surfaces and two long-side lateral surfaces. The two short-side lateral surfaces include a first external surface and a second external surface located on an opposite side from the first external surface. The two long-side lateral surfaces include a third external surface and a fourth external lateral surface located on an opposite side from the third external lateral surface. The lead is not exposed on the third external lateral surface nor the fourth external lateral surface. The first lead is exposed at the first external lateral surface and the second external lateral surface, respectively flush with the resin member at the first external lateral surface and the second external lateral surface. The second lead is exposed at the second external lateral surface, flush with the resin part at the second external lateral surface.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: November 24, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Ryohei Yamashita, Seitaro Akagawa, Toshiyuki Hashimoto, Kazuki Koda, Kiyoshi Kayama, Yuta Horikawa, Ryosuke Wakaki
  • Patent number: 10847480
    Abstract: A semiconductor package includes a substrate. At least a high-frequency chip and a circuit component susceptible to high-frequency interference are disposed on a top surface of the substrate. A first ground ring is disposed on the substrate surrounding the high-frequency chip. A first metal-post reinforced glue wall is disposed on the first ground ring surrounding the high-frequency chip. A second ground ring is disposed on the top of the substrate surrounding the circuit component. A second metal-post reinforced glue wall is disposed on the second ground ring surrounding the circuit component. A molding compound covers at least the high-frequency chip and the circuit component. A conductive layer is disposed on the molding compound and is coupled to the first metal-post reinforced glue wall and/or the second metal-post reinforced glue wall.
    Type: Grant
    Filed: January 1, 2019
    Date of Patent: November 24, 2020
    Inventor: Chung-Che Tsai
  • Patent number: 10836630
    Abstract: A MEMS package has a MEMS chip, and a package substrate which the MEMS chip is adhered. The MEMS chip has an element substrate which a movable element is formed. The MEMS package has a particle filter formed on the package substrate or the MEMS chip. The particle filter has a pierced-structure, which plural through holes are formed on a base surface by a regular arrangement. Further, in the particle filter, a plane-opening rate is set at least 45%, and a thickness-opening rate is set at least 50%.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: November 17, 2020
    Assignee: SAE Magnetics (H.K.) Ltd.
    Inventors: Masashi Shiraishi, Toyotaka Kobayashi, Hironobu Hayashi, Ichiro Yagi, Bing Ma
  • Patent number: 10840168
    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: November 17, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Tito Mangaoang
  • Patent number: 10840170
    Abstract: A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: November 17, 2020
    Assignee: HAESUNG DS CO., LTD.
    Inventors: In Seob Bae, Sung Il Kang
  • Patent number: 10829366
    Abstract: Disclosed is a method of forming an interconnect in a substrate having a first surface and a second surface. The method includes forming an insulating structure abutting the first surface and defining a closed loop around a via in the substrate and forming an insulating region abutting the second surface such that the insulating region contacts the insulating structure and separates the via from a bulk region of the substrate. Forming the insulating structure includes etching the substrate beginning from the first surface to form a trench, filling the trench to form a seam portion, and converting a first portion of the substrate to a first solid portion to form the closed loop.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: November 10, 2020
    Assignee: Kionix, Inc.
    Inventors: Scott G. Adams, Charles W. Blackmer
  • Patent number: 10825751
    Abstract: In semiconductor device, a substrate unit includes an insulating substrate, a first conductor substrate and a second conductor substrate which are disposed on one main surface of the insulating substrate and spaced apart from each other, and a third conductor substrate which is disposed on the other main surface opposite to the one main surface of the insulating substrate. A terminal is connected to a surface of a semiconductor element opposite to the first conductor substrate. The terminal extends from a region above the semiconductor element to a region above the second conductor substrate while being connected to the second conductor substrate. At least a part of the terminal, the substrate unit and the semiconductor element is sealed by a resin. The third conductor substrate is exposed from the resin.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 3, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakata, Tatsuya Kawase, Mikio Ishihara, Noboru Miyamoto
  • Patent number: 10825723
    Abstract: In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: November 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon Goo Hong, Harsono Simka, Mark Stephen Rodder
  • Patent number: 10818605
    Abstract: The circuit comprises at least one electronic chip (MT, MD), a laminated substrate and heat sink means, the chip being implanted in the substrate and the heat sink means being secured to opposing faces of the substrate. According to the invention, the heat sink means comprise heat-sink-forming bus-bars (BBH, BBL) mounted on the opposing faces of the substrate, each of said bus-bars being formed by a plurality of metal segments (BB1H, BB2H, BB3H, BB4H; BB1L, BB2L, BB3L) secured at spaced-apart positions and interconnected with one another and with a contact face of the electronic chip (MT, MD) by means of a metal layer (MEH, MEL).
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: October 27, 2020
    Assignees: INSTITUT VEDECOM, ELVIA PCB
    Inventors: Friedbald Kiel, Olivier Belnoue
  • Patent number: 10811279
    Abstract: A flip-chip manufacture is described. Methods of blocking adhesive underfill in flip-chip high speed component manufacture include creating topology discontinuities to prevent adhesive underfill material from interacting with RF sensitive regions on substrates.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 20, 2020
    Assignee: Ciena Corporation
    Inventors: Francois Pelletier, Michael Vitic