Patents Examined by Nitin Parekh
  • Patent number: 11961795
    Abstract: A semiconductor package that includes a support wiring structure. A semiconductor chip is on the support wiring structure. A cover wiring structure is on the semiconductor chip. A plurality of connection structures penetrates a filling member and electrically connects the support wiring structure to the cover wiring structure. The filling member fills a space between the support wiring structure and the cover wiring structure. The filling member surrounds the plurality of connection structures and the semiconductor chip and includes a plurality of fillers. A partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Bongken Yu
  • Patent number: 11955396
    Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device comprising the semiconductor assembly are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a carrier board. A plurality of first alignment solder parts are formed on a passive surface of the semiconductor device, and a plurality of corresponding second alignment solder parts are formed on the carrier board. The method further comprises forming a plurality of alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts whereby the semiconductor device is aligned and fixed to the carrier board; encapsulating the at least one semiconductor device to form a molded package body; sequentially forming a redistribution layer and external terminals on the molded package body so that the connection terminals are connected to the external terminal through the interconnection layer.
    Type: Grant
    Filed: November 26, 2021
    Date of Patent: April 9, 2024
    Assignee: Yibu Semiconductor Co., Ltd.
    Inventor: Weiping Li
  • Patent number: 11948862
    Abstract: Package structures and methods of forming package structures are described. A method includes placing a first package within a recess of a first substrate. The first package includes a first die. The method further includes attaching a first sensor to the first package and the first substrate. The first sensor is electrically coupled to the first package and the first substrate.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Hua Chen, Hao-Yi Tsai, Yu-Feng Chen
  • Patent number: 11935878
    Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: March 19, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsiu-Mei Yu, Guang-Yuan Jiang, Cheng-Yi Hsieh, Wei-Chan Chang, Chang-Sheng Lin
  • Patent number: 11935846
    Abstract: An electronic device includes a substrate, a first insulating film on the substrate, a second insulating film on the first insulating film, first and second coils respectively in the first and second insulating films, first and second terminals, and first and second connection conductors. The first and second insulating films contact each other so that the first and second coils are magnetically coupled. The first insulating film includes a first non-contact portion not contacting the second insulating film. One of the first and second insulating films includes a second non-contact portion not contacting the first or second insulating film. The first terminal is provided on the first non-contact portion and electrically connected to the first coil. The second terminal is provided on the second non-contact portion and electrically connected to the second coil. The first and second connection conductors are connected to the first and second terminals, respectively.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: March 19, 2024
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoichiro Kurita, Takanobu Kamakura, Masayuki Sugiura, Yoshiaki Aizawa
  • Patent number: 11923285
    Abstract: An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a circuit layer and an electronic component. The circuit layer includes a dielectric layer having an opening, and an electrical contact. A width of an aperture of the opening increases from a first surface toward a second surface. The electrical contact is at least partially disposed in the opening and exposed through the opening. The electronic component is disposed on the second surface and electrically connected to the circuit layer.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: March 5, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Po-Jen Cheng, Chien-Fan Chen
  • Patent number: 11916028
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant and a RDL structure, the encapsulant encapsulate sidewalls of the die. The RDL structure is disposed on the die and the encapsulant. The RDL structure includes a first dielectric structure and a first redistribution layer. The first dielectric structure includes a first dielectric material layer and a second dielectric material layer on the first dielectric material layer. The first redistribution layer is embedded in the first dielectric structure and electrically connected to the die, the redistribution layer comprises a first seed layer and a first conductive layer disposed on the first seed layer. A topmost surface of the first seed layer and a topmost surface of the first conductive layer are substantially level with a top surface of the second dielectric material layer.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Kuo-Chung Yee
  • Patent number: 11917829
    Abstract: A semiconductor memory device comprises a semiconductor substrate comprising a first region, a second region, and a third region provided therebetween. The first region comprises: first conductive layers; a first semiconductor layer facing the first conductive layers; and a second semiconductor layer connected to the first semiconductor layer. The second region comprises: a third semiconductor layer and fourth semiconductor layer; and a second conductive layer electrically connected to the third semiconductor layer, the fourth semiconductor layer, and the semiconductor substrate. The third region comprises a fifth semiconductor layer and sixth semiconductor layer that are formed continuously with the second semiconductor layer and the third semiconductor layer or fourth semiconductor layer, and extend in a second direction. The third region comprises first and second portions aligned alternately in the second direction.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Ayaka Takeoka, Yoshitaka Kubota
  • Patent number: 11901308
    Abstract: The present disclosure is directed to improving EMI shielding to provide more reliable semiconductor packages. The semiconductor package may be, for example, a lead frame including one or multiple dies attached thereto. The semiconductor package may include only wire bonds or a combination of clip bonds and wire bonds. An integrated shielding structure may be disposed in between the package substrate and the encapsulant to shield internal and/or external EMI. For example, a top surface of the integrated shield structure is exposed.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: February 13, 2024
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Il Kwon Shim, Kok Chuen Lock, Roel Adeva Robles, Eakkasit Dumsong
  • Patent number: 11894242
    Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, a molding member on the package substrate to cover at least a portion of the semiconductor chip, and a mechanical reinforcing member provided around the semiconductor chip within the molding member and extending in at least one direction.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO, LTD.
    Inventors: Taeyoung Kim, Seokhong Kwon, Wonyoung Kim, Jinchan Ahn
  • Patent number: 11887934
    Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: January 30, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park, Giorgio Cellere, Diego Tonini, Vincent DiCaprio, Kyuil Cho
  • Patent number: 11881413
    Abstract: A method for manufacturing electronic chips includes forming, on the side of a first face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed beforehand, metallizations coupling contacts of adjacent integrated circuits to one another. The method further includes forming, on the side of the first face of the substrate, first trenches extending through the first face of the substrate and laterally separating the adjacent integrated circuits. The first trenches extend through the metallizations to form at least a portion of metallizations at each of the adjacent circuits.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: January 23, 2024
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventors: Michael De Cruz, Olivier Ory
  • Patent number: 11881494
    Abstract: A semiconductor package and a method of manufacturing thereof is disclosed. The package includes a package substrate having a die attach region with a die attached thereto. A protective cover is disposed over a sensor region of the die and attached to the die by a cover adhesive. The package includes a dam structure configured to protect components of the semiconductor package from contamination.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: January 23, 2024
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Jeffrey Punzalan, Il Kwon Shim
  • Patent number: 11876083
    Abstract: Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongho Kim, Ji Hwang Kim, Hwan Pil Park, Jongbo Shim
  • Patent number: 11869863
    Abstract: A semiconductor device includes a substrate, an adhesive layer formed on a lower surface of the substrate, a semiconductor element adhered to a lower surface of the adhesive layer, a through hole extending through the substrate and the adhesive layer and exposing a first electrode arranged on an upper surface of the semiconductor element, a via wiring formed in the through hole, a wiring layer formed on an upper surface of the substrate and electrically connected to the first electrode through the via wiring, and a protective insulation layer formed on the lower surface of the adhesive layer. The protective insulation layer covers an entirety of all side surfaces of the semiconductor element and a peripheral part of a lower surface of the semiconductor element and exposes a central part of the lower surface of the semiconductor element.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: January 9, 2024
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Takashi Ito
  • Patent number: 11869823
    Abstract: Methods and structures for manufacturing one or more System in a Package (SiP) devices, where the functionality of a packaged SiP device may be modified by additional components.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: January 9, 2024
    Assignee: OCTAVO SYSTEMS LLC
    Inventors: Michael Kenneth Conti, Christopher Lloyd Reinert, Masood Murtuza
  • Patent number: 11862512
    Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
  • Patent number: 11862570
    Abstract: There is provided a semiconductor package capable of preventing damage to an interposer to improve reliability. The semiconductor package includes a first substrate including a first insulating layer and first conductive patterns, an interposer disposed on a top surface of the first substrate and including a second insulating layer and second conductive patterns, first connecting members in contact with the top surface of the first substrate and a bottom surface of the interposer, and supporting members including solder parts, which are in contact with the top surface of the first substrate and the bottom surface of the interposer, and core parts, which are disposed in the solder parts and include a different material from the solder parts. The first connecting members electrically connect the first conductive patterns and the second conductive patterns, and the supporting members do not electrically connect the first conductive patterns and the second conductive patterns.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Joo Kim, Sun Chul Kim, Min Keun Kwak, Hyun Ki Kim, Hyung Gil Baek, Yong Kwan Lee
  • Patent number: 11862574
    Abstract: A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filing at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jung Soo Kim
  • Patent number: 11862579
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: January 2, 2024
    Assignee: STMicroelectronics, Inc.
    Inventor: Ian Harvey Arellano