Patents Examined by Nitin Parekh
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Patent number: 12154886Abstract: A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.Type: GrantFiled: October 15, 2021Date of Patent: November 26, 2024Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Martin Gruber, Thorsten Scharf
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Patent number: 12132074Abstract: A package includes a first redistribution structure, a second redistribution structure, an inductor, a permalloy core, and a die. The second redistribution structure is over the first redistribution structure. The inductor includes a first portion, a second portion, and a third portion. The first portion is embedded in the first redistribution structure, the third portion is embedded in the second redistribution structure, and the second portion connects the first and third portions of the inductor. The permalloy core is located between the first and third portions of the inductor. The die is disposed adjacent to the second portion of the inductor.Type: GrantFiled: April 24, 2023Date of Patent: October 29, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Shiang Liao, Chih-Hang Tung
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Patent number: 12125784Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.Type: GrantFiled: August 17, 2023Date of Patent: October 22, 2024Assignee: Adeia Semiconductor Bonding Technologies Inc.Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, Jr., Jeremy Alfred Theil
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Patent number: 12125958Abstract: A solid state die such as an LED (or OLED) die that is fitted in a hole such as a through hole in a carrier substrate such as a PCB. The die is to be connected to the PCB e.g. to tracks on the PCB. The electrical contacts on the die are arranged to be (e.g. substantially) in the same plane as the contacts on the carrier substrate such as the PCB. This is achieved by the holes in the substrate such as the PCB being adapted so that the dies fit into the holes or openings, i.e. are each taken up into an opening before electrical contacts are made.Type: GrantFiled: October 28, 2019Date of Patent: October 22, 2024Assignee: BARCO N.V.Inventor: Chien Chih Liu
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Patent number: 12125741Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.Type: GrantFiled: August 1, 2023Date of Patent: October 22, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
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Patent number: 12116516Abstract: A metallic structure for an optical semiconductor device, including a base body having disposed thereon at least in part metallic layers in the following order; a nickel or nickel alloy plated layer, a gold or gold alloy plated layer, and a silver or silver alloy plated layer, wherein the silver or silver alloy plated layer has a thickness in a range of 0.001 ?m or more and 0.01 ?m or less.Type: GrantFiled: January 14, 2022Date of Patent: October 15, 2024Assignee: NICHIA CORPORATIONInventors: Yasuo Kato, Kazuya Matsuda
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Patent number: 12119321Abstract: A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad with a first bonding surface positioned away from the stack structure, and a second bonding pad; a carrier comprising a connecting surface; a third bonding pad which comprises a second bonding surface and is arranged on the connecting surface, and a fourth bonding pad arranged on the connecting surface of the carrier; and a conductive connecting layer comprising a first conductive part, comprising a first outer contour, and formed between and directly contacting the first bonding pad and the third bonding pad; a second conductive part formed between the second bonding pad and the fourth bonding pad; and a blocking part covering the first conductive part to form a covering area, wherein the first bonding surface comprises a first position which is the closest to the carrier within the covering area and a second position which is the farthest from the carrier within the covering area in a cross section vieType: GrantFiled: September 19, 2022Date of Patent: October 15, 2024Assignee: EPISTAR CORPORATIONInventors: Shih-An Liao, Shau-Yi Chen, Ming-Chi Hsu, Chun-Hung Liu, Min-Hsun Hsieh
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Patent number: 12119338Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.Type: GrantFiled: August 10, 2023Date of Patent: October 15, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
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Patent number: 12119219Abstract: A method of forming a group V metal nitride film on a substrate includes: providing the substrate within a processing container; and forming the group V metal nitride film on the substrate by alternately supplying, into the processing container, a raw material gas including a group V metal and a reducing gas including a nitrogen-containing gas.Type: GrantFiled: March 26, 2020Date of Patent: October 15, 2024Assignee: Tokyo Electron LimitedInventors: Hiroaki Ashizawa, Hideo Nakamura, Yosuke Serizawa, Yoshikazu Ideno
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Patent number: 12094764Abstract: A method for forming an interconnect structure is described. In some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.Type: GrantFiled: August 30, 2021Date of Patent: September 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Chin Lee, Hsiao-Kang Chang, Ting-Ya Lo, Chi-Lin Teng, Cherng-Shiaw Tsai, Shao-Kuan Lee, Kuang-Wei Yang, Hsin-Yen Huang, Shau-Lin Shue
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Patent number: 12080613Abstract: An electronic component module is provided that includes a substrate, an electronic component, a heat dissipating member, and a sealing resin. The electronic component is mounted on the substrate. The heat dissipating member includes a flat plate and columnar bodies. The sealing resin covers a side of a first main surface of the substrate and the electronic component. Moreover, the heat dissipating member, except for a top surface of the flat plate, is covered with the sealing resin. The columnar bodies are disposed at an outer peripheral of the flat plate, and have a shape protruding from a bottom surface of the flat plate. The columnar bodies include a root connected to the flat plate, and a tip connected to the substrate. In a plan view of the electronic component module, the tip is not outside the root.Type: GrantFiled: October 11, 2021Date of Patent: September 3, 2024Assignee: MURATA MANUFACTURING CO., LTD.Inventors: Motohiko Kusunoki, Osamu Yamaguchi, Shinichiro Banba, Takafumi Kusuyama
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Patent number: 12080625Abstract: A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.Type: GrantFiled: August 18, 2023Date of Patent: September 3, 2024Assignee: Infineon Technologies Austria AGInventors: Li Fong Chong, Yee Beng Daryl Yeow, Chii Shang Hong, Azlina Kassim, Hui Kin Lit
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Patent number: 12074118Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.Type: GrantFiled: June 13, 2023Date of Patent: August 27, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chia Hsiu Huang, Chun Chen Chen, Wei Chih Cho, Shao-Lun Yang
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Patent number: 12068173Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.Type: GrantFiled: May 22, 2023Date of Patent: August 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Hui Cheng, Szu-Wei Lu, Ping-Yin Hsieh, Chih-Hao Chen
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Patent number: 12068228Abstract: A leadless semiconductor package includes a conductive base having a plurality of apertures formed around a perimeter of the conductive base and extending from a first surface to an opposing second surface of the conductive base. The semiconductor package further includes an IC die having a third surface facing the first surface of the conductive base and having a plurality of conductive pillars disposed thereon. Each conductive pillar extends from the third surface to the first surface via a corresponding aperture. A dielectric fill material is disposed in the apertures and insulates the conductive pillars from the conductive material of the conductive base. An opening of an aperture at the second surface, the bottom end of the conductive pillar disposed therein, and the dielectric fill material at the opening of the aperture at the second surface together form a surface mount pad for mounting the semiconductor package to a corresponding pad of a circuit board.Type: GrantFiled: December 15, 2021Date of Patent: August 20, 2024Assignee: NXP USA, Inc.Inventor: Pat Lee
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Patent number: 12058101Abstract: Package structures and methods of forming package structures are described. A method includes placing a first package within a recess of a first substrate. The first package includes a first die. The method further includes attaching a first sensor to the first package and the first substrate. The first sensor is electrically coupled to the first package and the first substrate.Type: GrantFiled: August 8, 2023Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Chih-Hua Chen, Hao-Yi Tsai, Yu-Feng Chen
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Patent number: 12057361Abstract: A chip encapsulation structure, including: a wafer provided with a groove; a first metal wire arranged on surfaces of the groove and the wafer; a metal solder ball arranged on the first metal wire or on a metal pad of the chip, and is configured to solder the metal pad of the chip to the first metal wire; a first plastic encapsulation film covering upper surfaces of the wafer, the chip and the first metal wire, and entering a gap between a periphery of a functional area of the chip and the first metal wire, so as to form a closed cavity among the wafer, the groove and the chip; an inductive structure arranged on an upper surface of the first plastic encapsulation film and/or a lower surface of the wafer, and connected to the chip through the first metal wire; and a pad arranged on the inductive structure.Type: GrantFiled: May 28, 2019Date of Patent: August 6, 2024Assignee: Epicmems (Xiamen) Co., Ltd.Inventors: Wei Wang, Ping Li, Yanhao Peng, Nianchu Hu, Bin Jia
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Patent number: 12051618Abstract: The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure comprises: forming an interconnect layer and a conductive layer covered on a surface of the interconnect layer; forming a protective layer covering a surface of the conductive layer away from the interconnect layer; forming a trench penetrating the protective layer and the conductive layer; and filling a dielectric layer in the trench, and forming an air gap in the dielectric layer, the air gap extending from the trench in the conductive layer into the trench in the protective layer.Type: GrantFiled: February 8, 2021Date of Patent: July 30, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Nianwang Yang, Yuchen Wang
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Patent number: 12051633Abstract: A semiconductor device includes a semiconductor element, first and second leads, and a sealing resin. The semiconductor element includes first and second electrodes. The first lead includes a mounting base having a main face to which the first electrode is bonded and a back face, and includes a first terminal connected to the first electrode. The second lead includes a second terminal connected to the second electrode. The sealing resin includes a main face and a back face opposite to each other, and includes an end face oriented in the protruding direction of the terminals. The back face of the mounting base is exposed from the back face of the resin. The sealing resin includes a groove formed in its back face and disposed between the back face of the mounting base and a boundary between the second terminal and the end face of the resin.Type: GrantFiled: May 15, 2023Date of Patent: July 30, 2024Assignee: ROHM CO., LTD.Inventor: Koshun Saito
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Patent number: 12041772Abstract: A device includes a first region including first semiconductor pillars extending through first conductive layers; a second region including second semiconductor pillars extending through second conductive layers; and a third region disposed between the first region and the second region and including insulator columns extending through third conductive layers. The third region includes a fourth region and a fifth region. In the fourth region, one third conductive layer electrically connects one first conductive layer and one second conductive layer to each other, and in the fifth region, one third conductive layer is connected to a contact plug. A first diameter of a first subset of the insulator columns provided in the fourth region is smaller than a second diameter of a second subset of the insulator columns provided in the fifth region.Type: GrantFiled: August 26, 2021Date of Patent: July 16, 2024Assignee: KIOXIA CORPORATIONInventor: Hanae Ishihara