Abstract: A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

Abstract: An electronic device includes a die attach pad with a set of cantilevered first leads for down bond connections, a set of second leads spaced apart from the die attach pad, a semiconductor die mounted to the die attach pad and enclosed by a package structure, a set of first bond wires connected between respective bond pads of the semiconductor die and at least some of the first leads, and a set of second bond wires connected between respective further bond pads of the semiconductor die and at least some of the second leads.

Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.

Abstract: A semiconductor module includes a power element, a signal wiring, and a heat sink. The signal wiring is connected to a signal pad of the power element. The heat sink cools the power element. The power element has an active area provided by a portion where the signal pad is formed. The signal pad is thermally connected to the heat sink via the signal wiring.

Abstract: An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.

Abstract: According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate.

Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.

Abstract: A current sensor integrated circuit (IC) includes a unitary lead frame having at least one first lead having a terminal end, at least one second lead having a terminal end, and a paddle having a first surface and a second opposing surface. A semiconductor die is supported by the first surface of the paddle, wherein the at least one first lead is electrically coupled to the semiconductor die and the at least one second lead is electrically isolated from the semiconductor die. The current sensor IC further includes a first mold material configured to enclose the semiconductor die and the paddle and a second mold material configured to enclose at least a portion of the first mold material, wherein the terminal end of the at least one first lead and the terminal end of the at least one second lead are external to the second mold material.

Abstract: The disclosure describes a heat-dissipating object having a reservoir structure so that a reservoir system can be formed in an electronic device, allowing for a liquid TIM in the gap between the heat-dissipating object and the heat-generating object of the electronic device. The reservoir structure comprises a seal ring, a connecting hole and a reservoir which is a space for taking in a liquid material and releasing it again when needed. As a specific case of the heat-dissipating object and the electronic device, a lid having a reservoir structure and a lidded flip chip package based on the lid are particularly described in details of the embodiments of the present invention.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

Abstract: Techniques directed to forming and using coupling mechanisms for substrates, semiconductor packages, and/or printed circuit boards are described. One technique includes forming a substrate (205) comprising: first and second interconnect pads (213A, 213B) in or on a build-up layer (203); and first and second interconnects (211A, 211B) on the first and second interconnect pads (213A, 213B). The first interconnect pad (213A) can be located at a lower position than the second interconnect pad (213B) with regard to a z-position. The techniques described herein can assist with minimizing or eliminating solder ball bridge defects (SBBDs) that may be creating during performance of coupling technique (e.g., a reflow process, etc.).

Abstract: The present disclosure provides a packaging structure and a packaging method for an antenna. The packaging structure comprises a redistribution layer, having a first surface and an opposite second surface; a first metal joint pin, formed on the second surface of the redistribution layer; a first packaging layer, disposed on the redistribution layer covering the first metal joint pin; a first antenna metal layer, patterned on the first packaging layer, and a portion of the first antenna metal layer electrically connects with the first metal joint pin; a second metal joint pin, formed on the first antenna metal layer; a second packaging layer, disposed on the first antenna metal layer covering the second metal joint pin; a second antenna metal layer, formed on the second packaging layer; and a metal bump and an antenna circuit chip, bonded to the first surface of the redistribution layer.

Abstract: A semiconductor device includes a semiconductor element, first and second leads, and a sealing resin. The semiconductor element includes first and second electrodes. The first lead includes a mounting base having a main face to which the first electrode is bonded and a back face, and includes a first terminal connected to the first electrode. The second lead includes a second terminal connected to the second electrode. The sealing resin includes a main face and a back face opposite to each other, and includes an end face oriented in the protruding direction of the terminals. The back face of the mounting base is exposed from the back face of the resin. The sealing resin includes a groove formed in its back face and disposed between the back face of the mounting base and a boundary between the second terminal and the end face of the resin.

Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.

Abstract: A semiconductor element is mounted on a die pad, and electrode pads arranged along the outer circumference of an upper surface of the semiconductor element are electrically connected to leads by wires, respectively. The semiconductor element has an element region having a high sensitivity with respect to stress, and an element region having a relatively low sensitivity with respect to stress. A low-stress resin film is provided on the element region having a high sensitivity with respect to stress. The semiconductor element, the low-stress resin film, the die pad, and the leads are covered with an encapsulating resin.

Abstract: A semiconductor device has a substrate panel with a substrate having a first substrate area and a second substrate area outside a footprint of the first substrate area. A plurality of semiconductor die or discrete IPDs is disposed over the first substrate area. Substrate area 102a has electrical interconnect for the semiconductor die. A molding compound is disposed over the semiconductor die and first substrate area using a transfer mold process, which leaves mold culls and mold gates disposed over the second substrate area. A substrate edge is formed in the second substrate area under the mold gates. The substrate edge extends into the first substrate area under the molding compound to reinforce the mold gates and reduce cracking during mold degating. The substrate edge can have a variety of forms such as parallel bars, diagonal bars, orthogonal bars, and combinations thereof.

Abstract: Embodiments disclosed herein include an electronics package. In an embodiment, the electronics package comprises a package substrate and a die on the package substrate. In an embodiment, a mold layer is positioned over the package substrate. In an embodiment, the electronics package further comprises through-mold interconnects through the mold layer, and a trench that extends at least partially into the mold layer.

Abstract: A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die is coplanar with a bottom surface of the first encapsulating material. First dielectric layers are underlying the first device die. First redistribution lines are in the first dielectric layers and electrically coupling to the first device die. Second dielectric layers are overlying the first device die. Second redistribution lines are in the second dielectric layers and electrically coupling to the first redistribution lines. A second device die is overlying and electrically coupling to the second redistribution lines. No solder region connects the second device die to the second redistribution lines. A second encapsulating material encapsulates the second device die therein. A third device die is electrically coupled to the second redistribution lines. A third encapsulating material encapsulates the third device die therein.