Patents Examined by Nitin Parekh
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Patent number: 11776865Abstract: A semiconductor device and a method for manufacturing a semiconductor device that enable characteristics to be improved are provided. A semiconductor device includes a substrate that has a first surface and a second surface that is located opposite the first surface, a first element that is disposed on the first surface, and a first resin layer that is disposed on the first surface and that is disposed around the first element in a plan view. The substrate includes a wiring layer. The first element includes a semiconductor layer, an electrode portion that is located on a surface of the semiconductor layer facing the substrate, and an insulating layer that is located opposite the electrode portion with the semiconductor layer interposed therebetween. The electrode portion is connected to the wiring layer. A height of the first resin layer from the first surface is more than a height of the first element from the first surface.Type: GrantFiled: August 19, 2020Date of Patent: October 3, 2023Assignee: Murata Manufacturing Co., Ltd.Inventors: Teiji Yamamoto, Masayuki Aoike, Hiroyuki Nagai
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Patent number: 11776879Abstract: The present disclosure discloses a three-dimensional stacked package structure with a micro-channel heat dissipation structure and a packaging method thereof. The three-dimensional stacked package structure includes a chip package portion comprising a multi-layered structure with stacked chips, wherein the stacked chips are provided with through silicon vias and packaged in a three-dimensional stacked packaging manner and a silicon substrate package portion comprising a silicon substrate. The silicon substrate is provided with micro bumps which are to be interconnected with external lead wires. The chip package portion is assembled on the silicon substrate by bonding with the micro bumps. The stacked chips are etched with micro-channels and through holes corresponding to each other. The micro-channels are for coolant flowing in a horizontal direction, and the through holes are for coolant flowing in upper and lower layers. Sealing rings are arranged around the micro-channels and the through holes.Type: GrantFiled: April 25, 2023Date of Patent: October 3, 2023Assignee: ZHEJIANG LABInventors: Guandong Liu, Weihao Wang, Shunbin Li, Ruyun Zhang
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Patent number: 11764156Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.Type: GrantFiled: June 29, 2021Date of Patent: September 19, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hyunjae Song, Seunggeol Nam, Yeonchoo Cho, Seongjun Park, Hyeonjin Shin, Jaeho Lee
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Patent number: 11764126Abstract: An object of the present invention is to provide a semiconductor device whose surfaces on both sides can be cooled and which has a function of insulating, on both the surfaces, the internal structure of a semiconductor package from the outside. The semiconductor device includes a first semiconductor package and a second semiconductor package. The second semiconductor package is joined on the first semiconductor package in such a manner that a first exposed surface of the first semiconductor package and a fourth exposed surface of the second semiconductor package are connected so as to face each other, and a second exposed surface of the first semiconductor package and a third exposed surface of the second semiconductor package are connected so as to face each other.Type: GrantFiled: November 12, 2018Date of Patent: September 19, 2023Assignee: Mitsubishi Electric CorporationInventors: Hideo Komo, Takeshi Omaru, Takuya Tsuru
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Patent number: 11758654Abstract: The present invention discloses a circuit substrate including an insulation layer; a metal layer disposed on a first surface of the insulation layer; and a first solder pad and a second solder pad disposed on a second surface of the insulation layer opposite the metal layer. Shortest distances between soldering dots on the metal layer and a projected area of the first solder pad on the metal layer are shorter than a distance threshold, the shortest distance being a minimum value of vertical distances between each of the soldering dots on the metal layer and a side edge of the projected area of the first solder pad on the metal layer. The soldering dots on the metal layer correspond one-to-one to soldering dots on a corresponding die; and the side edge is adjacent to a projected area of the second solder pad on the metal layer.Type: GrantFiled: February 28, 2019Date of Patent: September 12, 2023Assignee: BITMAIN DEVELOPMENT PTE. LTD.Inventors: Tong Zou, Wenjie Cheng
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Patent number: 11756880Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.Type: GrantFiled: September 27, 2021Date of Patent: September 12, 2023Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, Jr., Jeremy Alfred Theil
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Patent number: 11756871Abstract: The present disclosure provides a fan-out packaging structure and a method for fabricating the fan-out packaging. The fan-out packaging structure includes a first redistribution layer, a second redistribution layer, metal connecting posts, a semiconductor chip, a first filling layer, a first packaging layer, a stacked chip package, a passive element, a second filling layer, a second packaging layer, and metal bumps. By means of the present disclosure, various chips having different functions can be integrated into one packaging structure, thereby improving the integration of the fan-out packaging structure. By means of the first redistribution layer, the second redistribution layer, and the metal connecting posts, a three-dimensional vertical stacked packaging is achieved.Type: GrantFiled: September 15, 2021Date of Patent: September 12, 2023Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATIONInventors: Yenheng Chen, Chengchung Lin
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Patent number: 11749621Abstract: An electronic device includes a die attach pad with a set of cantilevered first leads for down bond connections, a set of second leads spaced apart from the die attach pad, a semiconductor die mounted to the die attach pad and enclosed by a package structure, a set of first bond wires connected between respective bond pads of the semiconductor die and at least some of the first leads, and a set of second bond wires connected between respective further bond pads of the semiconductor die and at least some of the second leads.Type: GrantFiled: December 22, 2022Date of Patent: September 5, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ernesto Pentecostes Rafael, Jr., Dolores Babaran Milo, Michael Flores Milo
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Patent number: 11749576Abstract: A stacked package configuration is described that includes a bottom package and an upper package. The bottom package includes a substrate having a top surface with first circuitry and metal first pads. A molded layer is then formed over the substrate. Holes through the molded layer are then laser drilled to expose the first pads. The holes and first pads align with leads of an upper package, which contains further circuit components. The holes are then partially filled with a solder paste. A thermal epoxy is applied between the molded layer and the upper package. The leads of the upper package are then inserted into the holes, and the solder paste is reflowed to electrically, thermally, and mechanically connect the upper package to the bottom package. The reflow heat also cures the epoxy. A ball grid array is then formed on the bottom of the substrate.Type: GrantFiled: September 25, 2020Date of Patent: September 5, 2023Assignee: Analog Devices International Unlimited CompanyInventors: John D. Brazzle, Frederick E. Beville, David R. Ng, Michael J. Anderson, Yucheng Ying
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Patent number: 11749612Abstract: A semiconductor package device includes a flexible carrier, a first chip, a second chip, a first molding layer, a first adhesive layer and a second molding layer. The flexible carrier has a flexible layer and a rigid layer. The flexible layer has a patterned build-up circuit. The rigid layer is connected to a portion surface of the flexible layer. The position that the flexible layer connected to the rigid layer is formed a first carrying part and a second carrying part. The region of the flexible layer between the first carrying part and the second carrying part without the rigid layer is formed as a first flexible part. The first chip is connected to the first carrying part by flip-chip manner and the second chip is connected to the second carrying part by flip-chip manner. The first molding layer covers the first chip and the second molding layer covers the second chip. The first adhesive layer is connected between the first molding layer and the second carrying part.Type: GrantFiled: November 29, 2021Date of Patent: September 5, 2023Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chun-Hsien Yu, Shih-Ping Hsu, Hsien-Ming Tsai
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Patent number: 11749607Abstract: Provided are a package and a method of manufacturing the same. The package includes a first die, a second die, a bridge structure, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the bridge structure. The RDL structure is disposed over a backside of the bridge structure and the encapsulant. The RDL structure includes an insulating structure and a conductive pattern, the conductive pattern is disposed over the insulating structure and extending through the insulating structure and a substrate of the bridge structure, so as to form at least one through via in the substrate of the bridge structure.Type: GrantFiled: March 27, 2022Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Wu, Chen-Hua Yu, Kuo-Chung Yee, Szu-Wei Lu, Ying-Ching Shih
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Patent number: 11735571Abstract: A semiconductor package includes: a first wiring pattern; a dielectric layer that covers the first wiring pattern; a second wiring pattern on the dielectric layer, wherein the second wiring pattern includes a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern; a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes a connection part and an extension part, wherein the connection part covers a first surface of the line part of the second wiring pattern, and the extension part has a top surface at a level lower than a level of the top surface of the line part of the second wiring pattern; and a seed pattern between the extension part and the dielectric layer.Type: GrantFiled: May 17, 2021Date of Patent: August 22, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Yonghwan Kwon
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Patent number: 11728235Abstract: A semiconductor device and a method for manufacturing a semiconductor device that enable characteristics to be improved are provided. A semiconductor device includes a substrate that has a first surface and a second surface that is located opposite the first surface, a first element that is disposed on the first surface, and a first resin layer that is disposed on the first surface and that is disposed around the first element in a plan view. The substrate includes a wiring layer. The first element includes a semiconductor layer, an electrode portion that is located on a surface of the semiconductor layer facing the substrate, and an insulating layer that is located opposite the electrode portion with the semiconductor layer interposed therebetween. The electrode portion is connected to the wiring layer. A height of the first resin layer from the first surface is more than a height of the first element from the first surface.Type: GrantFiled: August 19, 2020Date of Patent: August 15, 2023Assignee: Murata Manufacturing Co., Ltd.Inventors: Teiji Yamamoto, Masayuki Aoike, Hiroyuki Nagai
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Patent number: 11716816Abstract: This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.Type: GrantFiled: June 30, 2021Date of Patent: August 1, 2023Assignee: IMBERATEK, LLCInventors: Antti Iihola, Timo Jokela
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Patent number: 11710674Abstract: Various embodiments disclosed relate to a substrate for a semiconductor device. The substrate includes a first major surface and a second major surface opposite the first major surface. The substrate further includes a cavity defined by a portion of the first major surface. The cavity includes a bottom dielectric surface and a plurality of sidewalls extending from the bottom surface to the first major surface. A first portion of a first sidewall includes a conductive material.Type: GrantFiled: March 29, 2022Date of Patent: July 25, 2023Assignee: Intel CorporationInventors: Yi Elyn Xu, Bilal Khalaf, Dennis Sean Carr
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Patent number: 11699597Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.Type: GrantFiled: July 29, 2021Date of Patent: July 11, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Hui Cheng, Szu-Wei Lu, Ping-Yin Hsieh, Chih-Hao Chen
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Patent number: 11696407Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.Type: GrantFiled: December 22, 2021Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Chong Zhang, Ying Wang, Junnan Zhao, Cheng Xu, Yikang Deng
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Patent number: 11688704Abstract: An integrated circuit package and a system including the integrated circuit package as well as a process for assembling the integrated circuit package are provided to improve integrated circuit power delivery. The integrated circuit package includes a first die having a plurality of pads formed in the first die and exposed on a top surface of the first die, at least one post on the first die, and a substrate including one or more redistribution layers. Each post in the at least one post spans at least two pads on the first die utilized for power distribution, and the first die is connected to the substrate via the at least one post.Type: GrantFiled: January 21, 2022Date of Patent: June 27, 2023Assignee: Futurewei Technologies, Inc.Inventors: Shiqun Gu, Jinghua Zhu, Hongying Zhang, Jun Xia, Wangsheng Xie, Shuangfu Wang, Hong Liu, Liming Zhao, Hongquan Sun
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Patent number: 11676890Abstract: A semiconductor package that includes a support wiring structure. A semiconductor chip is on the support wiring structure. A cover wiring structure is on the semiconductor chip. A plurality of connection structures penetrates a filling member and electrically connects the support wiring structure to the cover wiring structure. The filling member fills a space between the support wiring structure and the cover wiring structure. The filling member surrounds the plurality of connection structures and the semiconductor chip and includes a plurality of fillers. A partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level.Type: GrantFiled: March 11, 2021Date of Patent: June 13, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Bongken Yu
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Patent number: 11676919Abstract: An electronic device includes a substrate, a first insulating film on the substrate, a second insulating film on the first insulating film, first and second coils respectively in the first and second insulating films, first and second terminals, and first and second connection conductors. The first and second insulating films contact each other so that the first and second coils are magnetically coupled. The first insulating film includes a first non-contact portion not contacting the second insulating film. One of the first and second insulating films includes a second non-contact portion not contacting the first or second insulating film. The first terminal is provided on the first non-contact portion and electrically connected to the first coil. The second terminal is provided on the second non-contact portion and electrically connected to the second coil. The first and second connection conductors are connected to the first and second terminals, respectively.Type: GrantFiled: March 5, 2021Date of Patent: June 13, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Yoichiro Kurita, Takanobu Kamakura, Masayuki Sugiura, Yoshiaki Aizawa