Patents Examined by Nitin Parekh
  • Patent number: 11676890
    Abstract: A semiconductor package that includes a support wiring structure. A semiconductor chip is on the support wiring structure. A cover wiring structure is on the semiconductor chip. A plurality of connection structures penetrates a filling member and electrically connects the support wiring structure to the cover wiring structure. The filling member fills a space between the support wiring structure and the cover wiring structure. The filling member surrounds the plurality of connection structures and the semiconductor chip and includes a plurality of fillers. A partial portion of the plurality of fillers includes cutting fillers having a flat surface that extends along a vertical level that is a reference level.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: June 13, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Bongken Yu
  • Patent number: 11676919
    Abstract: An electronic device includes a substrate, a first insulating film on the substrate, a second insulating film on the first insulating film, first and second coils respectively in the first and second insulating films, first and second terminals, and first and second connection conductors. The first and second insulating films contact each other so that the first and second coils are magnetically coupled. The first insulating film includes a first non-contact portion not contacting the second insulating film. One of the first and second insulating films includes a second non-contact portion not contacting the first or second insulating film. The first terminal is provided on the first non-contact portion and electrically connected to the first coil. The second terminal is provided on the second non-contact portion and electrically connected to the second coil. The first and second connection conductors are connected to the first and second terminals, respectively.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: June 13, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoichiro Kurita, Takanobu Kamakura, Masayuki Sugiura, Yoshiaki Aizawa
  • Patent number: 11676912
    Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a substrate, a clip, and a support structure. The clip is disposed on the substrate. The clip includes a first portion and a second portion separated from each other by a slit. The support structure is above the substrate and supports the clip. The support structure has a first surface and a second surface facing the first surface, and the first surface and the second surface define a gap.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 13, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia Hsiu Huang, Chun Chen Chen, Wei Chih Cho, Shao-Lun Yang
  • Patent number: 11670670
    Abstract: A manufacturing method of a package includes at least the following steps. A carrier is provided. An inductor is formed over the carrier. The inductor includes a first portion, a second portion, and a third portion. The first portion is parallel to the third portion, and the second portion connects the first portion and the third portion. A die is placed over the carrier. The die is surrounded by the inductor. An encapsulant is formed between the first portion and the third portion of the inductor. The encapsulant laterally encapsulates the die and the second portion of the inductor.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Shiang Liao, Chih-Hang Tung
  • Patent number: 11670573
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a redistribution layer including a first conductive feature and a second conductive feature, a first contact feature disposed over and electrically coupled to the first conductive feature, a second contact feature disposed over and electrically coupled to the second conductive feature, and a passivation feature extending from between the first conductive feature and the second conductive feature between the first contact feature and the second contact feature. The passivation feature includes a dielectric feature and a dielectric layer. The dielectric layer is disposed on a planar top surface of the dielectric feature and a composition of the dielectric feature is different from a composition of the dielectric layer.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Chun-Li Lin, Dian-Hau Chen
  • Patent number: 11658098
    Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: May 23, 2023
    Assignee: STMicroelectronics, Inc.
    Inventors: Jefferson Talledo, Tito Mangaoang
  • Patent number: 11652018
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
  • Patent number: 11646498
    Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a cavity resonator antenna over the first conductive layer and substrate. The cavity resonator antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the cavity resonator antenna, first conductive layer, and substrate. The conductive cavity may extend vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: May 9, 2023
    Assignee: Intel Corporation
    Inventors: Kilian Roth, Sonja Koller, Josef Hagn, Andreas Wolter, Andreas Augustin
  • Patent number: 11646255
    Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo Lung Pan, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu, Po-Yuan Teng, Teng-Yuan Lo, Mao-Yen Chang
  • Patent number: 11631623
    Abstract: A lead member includes a plurality of lead terminals, and the lead terminals extend from the inside to the outside of a mold resin. Each of the lead terminals has a base portion and a tip end portion on the outside of the mold resin. The base portion is disposed on a region side having a semiconductor element and extends in a direction protruding from the mold resin. The tip end portion extends in a direction different from the base portion and is disposed on the opposite side to a region having the semiconductor element as viewed from the base portion. The length by which the base portion extends differs between a pair of lead terminals adjacent to each other, among the lead terminals. At least a surface of the base portion of each of the lead terminals is covered with a coating resin.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 18, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takamasa Iwai, Junji Fujino, Hiroshi Kawashima
  • Patent number: 11631626
    Abstract: A package structure includes a first circuit board, a second circuit board, at least one electronic component, at least one conductive lead, and a molding compound. The first circuit board includes a first circuit layer and a second circuit layer. The second circuit board includes a third circuit layer and a fourth circuit layer. The electronic component is disposed between the first circuit board and the second circuit board. The conductive lead contacts at least one of the second circuit layer and the third circuit layer. The conductive lead has a vertical height, and the vertical height is greater than a vertical distance between the second circuit layer and the third circuit layer. The molding compound covers the first circuit board, the second circuit board, the electronic component, and the conductive lead. The molding compound exposes the first circuit layer and the fourth circuit layer, and the conductive lead extends outside the molding compound.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: April 18, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Ra-Min Tain, Po-Hsiang Wang, Chi-Chun Po
  • Patent number: 11626393
    Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.
    Type: Grant
    Filed: February 19, 2021
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Lim Suk, Seokhyun Lee
  • Patent number: 11626335
    Abstract: Embodiments of the present disclosure provide an IC packaging structure and an IC packaging method, relating to the chip packaging field. The IC packaging structure includes: a substrate, a stress buffer sheet mounted on the substrate; a packaged chip mounted on the stress buffer sheet, and a plastic package body coated outside the packaged chip, wherein the packaged chip is electrically connected to the substrate, and the stress buffer sheet is used for buffering stress acting on the packaged chip. Compared with the prior art, in the IC packaging structure provided in the present disclosure, the stress buffer sheet is mounted on the substrate through silver glue, the packaged chip is mounted on the stress buffer sheet through silver glue.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: April 11, 2023
    Assignee: Forehope Electronic (Ningbo) Co., Ltd.
    Inventors: Shunbo Wang, Lei Zhong
  • Patent number: 11621231
    Abstract: Leadless power amplifier (PA) packages and methods for fabricating leadless PA packages having topside terminations are disclosed. In embodiments, the method includes providing electrically-conductive pillar supports and a base flange. At least a first radio frequency (RF) power die is attached to a die mount surface of the base flange and electrically interconnected with the pillar supports. Pillar contacts are further provided, with the pillar contacts electrically coupled to the pillar supports and projecting therefrom in a package height direction. The first RF power die is enclosed in a package body, which at least partially defines a package topside surface opposite a lower surface of the base flange. Topside input/out terminals are formed, which are accessible from the package topside surface and which are electrically interconnected with the first RF power die through the pillar contacts and the pillar supports.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: April 4, 2023
    Assignee: NXP USA, Inc.
    Inventors: Yun Wei, Fernando A. Santos, Lakshminarayan Viswanathan, Scott Duncan Marshall
  • Patent number: 11621204
    Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: April 4, 2023
    Assignee: Infineon Technologies AG
    Inventors: Oliver Markus Kreiter, Ludwig Busch, Angel Enverga, Mei Fen Hiew, Tian See Hoe, Elvis Keli, Kean Ming Koe, Sanjay Kumar Murugan, Michael Niendorf, Ivan Nikitin, Bernhard Stiller, Thomas Stoek, Ke Yan Tean
  • Patent number: 11610786
    Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, a molding member on the package substrate to cover at least a portion of the semiconductor chip, and a mechanical reinforcing member provided around the semiconductor chip within the molding member and extending in at least one direction.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: March 21, 2023
    Assignee: SAMSUNG ELECTRONICS., CO., LTD.
    Inventors: Taeyoung Kim, Seokhong Kwon, Wonyoung Kim, Jinchan Ahn
  • Patent number: 11594520
    Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Cheng-Chieh Hsieh, Ming-Yen Chiu
  • Patent number: 11581263
    Abstract: A semiconductor package includes: a redistribution layer including a plurality of redistribution insulating layers, a plurality of redistribution line patterns that constitute lower wiring layers, and a plurality of redistribution vias that are connected to some of the plurality of redistribution line patterns while penetrating at least one of the plurality of redistribution insulating layers; at least one semiconductor chip arranged on the redistribution layer; an expanded layer surrounding the at least one semiconductor chip on the redistribution layer; and a cover wiring layer including at least one base insulating layer, a plurality of wiring patterns that constitute upper wiring layers, and a plurality of conductive vias that are connected to some of the plurality of wiring patterns while penetrating the at least one base insulating layer.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: February 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Choongbin Yim, Jungwoo Kim, Jihwang Kim, Jungsoo Byun, Jongbo Shim, Doohwan Lee, Kyoungsei Choi, Junggon Choi, Sungeun Pyo
  • Patent number: 11581240
    Abstract: An integrated circuit package that includes a liquid phase thermal interface material (TIM) is described. The package may include any number of die. The liquid phase TIM can be sealed in a chamber between a die and an integrated heat spreader and bounded on the sides by a perimeter layer. The liquid phase TIM can be fixed in place or circulated, depending on application. A thermal conductivity of the liquid phase TIM can be at least 15 Watts/meter-Kelvin, according to some embodiments. A liquid phase TIM eliminates failure mechanisms present in solid phase TIMs, such as cracking due to warpage and uncontained flow out of the module.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Kedar Dhane, Omkar Karhade, Aravindha R. Antoniswamy, Divya Mani
  • Patent number: 11574924
    Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure and a center filling layer, wherein the metal dielectric layer in the opening is interfaced with the conductive structure.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: February 7, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Changseok Kang, Tomohiko Kitajima