Abstract: Methods for forming semiconductor die assemblies with heat transfer features are disclosed herein. In some embodiments, the methods comprise providing a wafer having a first side and a second side opposite the first side, attaching a semiconductor die stack to the first side of the wafer, and forming a plurality of heat transfer features at the second side of the wafer. The heat transfer features can be defined by a plurality of grooves that define an exposed continuous surface of the wafer at the second side compared to a planar surface of the wafer.

Abstract: A semiconductor device comprises a semiconductor die, comprising a stacking structure, a first bonding pad with a first bonding surface positioned away from the stacking structure, and a second bonding pad; a carrier comprising a connecting surface; a third bonding pad which comprises a second bonding surface and is arranged on the connecting surface, and a fourth bonding pad arranged on the connecting surface; and a conductive connecting layer comprising a first conducting part, comprising a first outer boundary, and formed between and directly contacting the first bonding pad and the third bonding pad; a second conducting part formed between the second bonding pad and the fourth bonding pad; and a blocking part covering the first conducting part.

Abstract: In a described example, a packaged device includes a substrate having a device mounting surface including a first layer of conductive material having a first thickness less than a substrate thickness, the substrate having a second layer of the conductive material having a second thickness less than the substrate thickness. A first semiconductor device is mounted to a first area of the device mounting surface; and a second semiconductor device is mounted to a second area on the device mounting surface and spaced from the first semiconductor device. At least two connectors are formed of the first layer of the substrate having first ends coupled to one of first bond pads on the first semiconductor device and the at least two connectors having second ends coupled to one of second bond pads on the second semiconductor device.

Abstract: A semiconductor device having a housing is provided, where the housing includes the first surface, concave portions provided to the first surface, the second surface to face toward the first surface, and convex portions provided in contact with the second surface. In a thickness direction of the housing directed from the first surface to the second surface, the concave portions and the convex portions are provided at positions corresponding to each other.

Abstract: To provide a semiconductor package including a protruding part at the bottom surface of a package main body. A semiconductor package including a semiconductor chip is provided, the semiconductor package including: a package main body; a plurality of electrodes exposed at a bottom surface of the package main body; and a protruding part projecting from the bottom surface of the package main body and above the plurality of electrodes, wherein the protruding part is arranged not to overlap two least separated electrodes, among the plurality of electrodes, in a second direction different from a first direction in which the two electrodes are arrayed.

Abstract: A package structure including first and second packages is provided. The first package includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, and a plurality of conductive wire segments. The semiconductor die has an active surface and a back surface. The insulating encapsulant encapsulates the semiconductor die. The first redistribution layer is disposed on the back surface of the semiconductor die and a bottom surface of the insulating encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The second redistribution layer is disposed on the active surface of the semiconductor die. The plurality of conductive wire segments electrically connects the semiconductor die to the second redistribution layer and the first redistribution layer to the second redistribution layer. The second package is stacked on the second surface of the first redistribution layer over the first package.

Abstract: According to one embodiment, a semiconductor device includes a first board including a plurality of terminals, a semiconductor chip flip-chip mounted to the first board, and an insulating layer covering the first board and the semiconductor chip. The plurality of terminals include at least one first terminal electrically connected to the semiconductor chip, and at least one second terminal that is not connected to the semiconductor chip, wherein the at least one second terminal is not covered by the insulating layer.

Abstract: A light emitting device includes one or more light emitting elements; a first lead on which the one or more light emitting elements are disposed; a second lead electrically connected to the one or more light emitting elements; a resin member supporting the first lead and the second lead, and including one or more projected portions; and a resin frame surrounding the light emitting elements, and covering at least a portion of each of the projected portions.

Abstract: A method of processing a double sided wafer of a microelectromechanical device includes spinning a resist onto a first side of a first wafer. The method further includes forming pathways within the resist to expose portions of the first side of the first wafer. The method also includes etching one or more depressions in the first side of the first wafer through the pathways, where each of the depressions have a planar surface and edges. Furthermore, the method includes depositing one or more adhesion metals over the resist such that the one or more adhesion metals are deposited within the depressions, and then removing the resist from the first wafer. The method finally includes depositing indium onto the adhesion metals deposited within the depressions and bonding a second wafer to the first wafer by compressing the indium between the second wafer and the first wafer.

Abstract: A semiconductor package device comprises a substrate, an electrical component and a package body. The electrical component is disposed on the substrate. The electrical component has an active surface facing toward the substrate and a back surface opposite to the active surface. The back surface has a first portion and a second portion surrounding the first portion. The first portion of the back surface of the electrical component includes a plurality of pillars. The package body is disposed on the substrate. The package body encapsulates the electrical component and exposes the back surface of the electrical component.

Abstract: An arrangement including a carrier substrate, and a component situated on a cover surface of the carrier substrate in a hollow space, and electrical contacts for the component, wherein the hollow space is comprised of a plurality of spacer elements arranged on the cover surface of the carrier substrate and a cover substrate mounted on the plurality of spacer elements is provided. A semi-finished product comprising a carrier substrate made of silicon, wherein one or more recesses are formed on one side of the carrier substrate, and wherein the semi-finished product further comprises an alkaline evaporated glass applied to the side of the carrier substrate having the one or more recesses is also provided.

Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

Abstract: In a described example, an integrated circuit (IC) package includes: an IC chip bonded to a chip mount pad on a lead frame; low modulus molding compound surrounding the IC chip; and IC package molding compound covering the IC chip, and at least a portion of the low modulus molding compound.

Abstract: Micro LED and microdriver chip integration schemes are described. In an embodiment a microdriver chip includes a plurality of trenches formed in a bottom surface of the microdriver chip, with each trench surrounding a conductive stud extending below a bottom surface of the microdriver chip body. Integration schemes are additionally described for providing electrical connection to conductive terminal contacts and micro LEDs bonded to a display substrate and adjacent to a microdriver chip.

Abstract: A joined body according to the invention is a ceramic/aluminum joined body including: a ceramic member; and an aluminum member made of aluminum or an aluminum alloy, in which the ceramic member and the aluminum member are joined to each other, the ceramic member is formed of silicon nitride containing magnesium, and a joining layer in which magnesium is contained in an aluminum-silicon-oxygen-nitrogen compound is formed at a joining interface between the ceramic member and the aluminum member.

Abstract: A semiconductor device that reduces the deformation of a metal base due to pressure during transfer molding, to thereby suppress the occurrence of cracks in an insulating layer to achieve high electrical reliability. The semiconductor device includes: a metal member provided, on its lower surface, with a projection and a depression, and a projecting peripheral portion surrounding the projection and the depression and having a height greater than or equal to a height of the projection of the projection and the depression; an insulating layer formed on an upper surface of the metal member; a metal layer formed on an upper surface of the insulating layer; a semiconductor element joined to an upper surface of the metal layer; and a sealing resin to seal the semiconductor element, the metal layer, the insulating layer and the metal member.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a first encapsulant, a second encapsulant, a protection layer, a RDL structure and a connector. The first encapsulant is aside a first sidewall of the die, at least encapsulating a portion of the first sidewall of the die. The second encapsulant is aside a second sidewall of the die, encapsulating the second sidewall of the die. The protection layer is aside the first sidewall of the die and on the first encapsulant. The RDL structure is on a first surface of the die. The connector is electrically connected to the die through the RDL structure.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads; and an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip.

Abstract: A semiconductor device package includes a buffer layer having an upper surface perpendicular to a first direction, a plurality of semiconductor chips stacked on the buffer layer one by one in the first direction, and a chip sealing material surrounding sidewalls of the semiconductor chips. The semiconductor chips include an upper semiconductor chip at a farthest position from the buffer layer and a remaining plurality of intermediate semiconductor chips. Each of the intermediate semiconductor chips includes through silicon vias (TSVs) passing through each of the intermediate semiconductor chips. The upper semiconductor chip includes a trench formed in at least a portion of a periphery of the upper semiconductor chip and covered by the chip sealing material. Accordingly, the semiconductor device package provides increased device reliability.