Abstract: A light emitting device includes a resin package having a rectangular shape in a top view and two short-side lateral surfaces and two long-side lateral surfaces. The two short-side lateral surfaces include a first external surface and a second external surface located on an opposite side from the first external surface. The two long-side lateral surfaces include a third external surface and a fourth external lateral surface located on an opposite side from the third external lateral surface. The lead is not exposed on the third external lateral surface nor the fourth external lateral surface. The first lead is exposed at the first external lateral surface and the second external lateral surface, respectively flush with the resin member at the first external lateral surface and the second external lateral surface. The second lead is exposed at the second external lateral surface, flush with the resin part at the second external lateral surface.

Abstract: A semiconductor package includes a substrate. At least a high-frequency chip and a circuit component susceptible to high-frequency interference are disposed on a top surface of the substrate. A first ground ring is disposed on the substrate surrounding the high-frequency chip. A first metal-post reinforced glue wall is disposed on the first ground ring surrounding the high-frequency chip. A second ground ring is disposed on the top of the substrate surrounding the circuit component. A second metal-post reinforced glue wall is disposed on the second ground ring surrounding the circuit component. A molding compound covers at least the high-frequency chip and the circuit component. A conductive layer is disposed on the molding compound and is coupled to the first metal-post reinforced glue wall and/or the second metal-post reinforced glue wall.

Abstract: A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.

Abstract: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.

Abstract: A MEMS package has a MEMS chip, and a package substrate which the MEMS chip is adhered. The MEMS chip has an element substrate which a movable element is formed. The MEMS package has a particle filter formed on the package substrate or the MEMS chip. The particle filter has a pierced-structure, which plural through holes are formed on a base surface by a regular arrangement. Further, in the particle filter, a plane-opening rate is set at least 45%, and a thickness-opening rate is set at least 50%.

Abstract: Disclosed is a method of forming an interconnect in a substrate having a first surface and a second surface. The method includes forming an insulating structure abutting the first surface and defining a closed loop around a via in the substrate and forming an insulating region abutting the second surface such that the insulating region contacts the insulating structure and separates the via from a bulk region of the substrate. Forming the insulating structure includes etching the substrate beginning from the first surface to form a trench, filling the trench to form a seam portion, and converting a first portion of the substrate to a first solid portion to form the closed loop.

Abstract: In semiconductor device, a substrate unit includes an insulating substrate, a first conductor substrate and a second conductor substrate which are disposed on one main surface of the insulating substrate and spaced apart from each other, and a third conductor substrate which is disposed on the other main surface opposite to the one main surface of the insulating substrate. A terminal is connected to a surface of a semiconductor element opposite to the first conductor substrate. The terminal extends from a region above the semiconductor element to a region above the second conductor substrate while being connected to the second conductor substrate. At least a part of the terminal, the substrate unit and the semiconductor element is sealed by a resin. The third conductor substrate is exposed from the resin.

Abstract: In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.

Abstract: The circuit comprises at least one electronic chip (MT, MD), a laminated substrate and heat sink means, the chip being implanted in the substrate and the heat sink means being secured to opposing faces of the substrate. According to the invention, the heat sink means comprise heat-sink-forming bus-bars (BBH, BBL) mounted on the opposing faces of the substrate, each of said bus-bars being formed by a plurality of metal segments (BB1H, BB2H, BB3H, BB4H; BB1L, BB2L, BB3L) secured at spaced-apart positions and interconnected with one another and with a contact face of the electronic chip (MT, MD) by means of a metal layer (MEH, MEL).

Abstract: A flip-chip manufacture is described. Methods of blocking adhesive underfill in flip-chip high speed component manufacture include creating topology discontinuities to prevent adhesive underfill material from interacting with RF sensitive regions on substrates.

Abstract: This publication discloses an electronic module, comprising a first conductive pattern layer and a first insulating-material layer on at least one surface of the first conductive pattern layer, at least one opening in the first insulating-material layer that extends through the first insulating-material layer, a component having a contact surface with contact terminals, the component being arranged at least partially within the opening with its contact terminals electrically coupled to the first conductive pattern layer, a second insulating-material layer provided on the first insulating-material layer, and a conductive pattern embedded between the first and second insulating material layers. This publication additionally discloses a method for manufacturing an electronic module.

Abstract: Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.

Abstract: A method of fabricating an INFO package may include at least the following steps. A first buffer pattern and a second buffer pattern are formed on a substrate. A first chip is attached on the substrate through the first buffer pattern. A second chip is attached on the substrate through the second buffer pattern. A squeezing force is provided between an exterior surface of the substrate and a top surface of the first chip and between an exterior surface of the substrate and a top surface of the second chip. The squeezed first buffer pattern and the squeezed second buffer pattern are cured. A molding compound is formed surrounding the first chip, the second chip, the squeezed first buffer pattern and the squeezed second buffer pattern. A redistribution circuit structure layer is formed electrically connected to the first chip and the second chip on the molding compound.

Abstract: A semiconductor package includes an electrically insulating first encapsulant body having an upper surface, a first semiconductor die encapsulated within the first encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the first encapsulant body, a plurality of electrically conductive leads, each of the leads having interior ends that are encapsulated within the first encapsulant body and outer ends that are exposed from the first encapsulant body, and a first direct electrical connection between the first conductive pad and the interior end of a first lead from the plurality. The first direct electrical connection includes a first conductive track formed in the upper surface of the first encapsulant body. The first encapsulant body includes a laser activatable mold compound. The first conductive track is formed in a first laser activated region of the laser activatable mold compound.

Abstract: An electronic device includes an electronic element, a plurality of first sub-electrodes arrayed in a first direction, a plurality of second sub-electrodes arrayed in a second direction that is orthogonal to the first direction, a dummy electrode, and a sealing resin. The sealing resin has a resin back surface from which the plurality of first sub-electrodes, the plurality of second sub-electrodes and the dummy electrode are exposed. The plurality of second sub-electrodes are located further in the first direction than any of the plurality of first sub-electrodes. The plurality of first sub-electrodes are located further in the second direction than any of the plurality of second sub-electrodes. The dummy electrode is located further in the first direction than any of the plurality of first sub-electrodes, and is located further in the second direction than any of the plurality of second sub-electrodes.

Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.

Abstract: A method of manufacturing a package structure includes the following processes. An adhesive layer is formed on a carrier. A die is attached to the carrier through the adhesive layer. A protection layer is formed to at least cover a sidewall and a portion of a top surface of the adhesive layer on an edge of the carrier. An encapsulant is formed over the carrier to laterally encapsulate the die. A redistribution layer (RDL) structure is formed on the die and the encapsulant. A connector is formed to electrically connect to the die through the RDL structure. The carrier is released.

Abstract: A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die is coplanar with a bottom surface of the first encapsulating material. First dielectric layers are underlying the first device die. First redistribution lines are in the first dielectric layers and electrically coupling to the first device die. Second dielectric layers are overlying the first device die. Second redistribution lines are in the second dielectric layers and electrically coupling to the first redistribution lines. A second device die is overlying and electrically coupling to the second redistribution lines. No solder region connects the second device die to the second redistribution lines. A second encapsulating material encapsulates the second device die therein. A third device die is electrically coupled to the second redistribution lines. A third encapsulating material encapsulates the third device die therein.

Abstract: The present disclosure provides an antenna package structure and packaging method. The package structure includes: a metal joint pin fabricated by using a wire bonding process; and a packaging layer, covering the metal joint pin. An antenna circuit chip and an antenna metal layer are electrically connected to two ends of the antenna feeder package structure.

Abstract: A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.