Patents Examined by Nitin Parekh
  • Semiconductor device package
    Patent number: 10770369
    Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a heat dissipation lid and a thermal isolation. The substrate has a surface. The first electronic component and the second electronic component are over the surface of the substrate and arranged along a direction substantially parallel to the surface. The first electronic component and the second electronic component are separated by a space therebetween. The heat dissipation lid is over the first electronic component and the second electronic component. The heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component. The thermal isolation is in the one or more apertures of the heat dissipation lid.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: September 8, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Pin Hung, Tang-Yuan Chen, Jin-Feng Yang, Meng-Kai Shih
  • Semiconductor package and manufacturing method of the same
    Patent number: 10770437
    Abstract: The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged die having a carrier surface and a molding surface, and a first die structure in proximity to the carrier surface. An active region of the first die structure is electrically coupled to the packaged die through a solder. The second layer includes a second die structure, the second die structure being connected to the active region of the first die structure by a first redistributed layer (RDL). The conductive array is connected to an active region of the second die structure by a second RDL. The present disclosure also provides a method for manufacturing the aforesaid semiconductor package.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jui-Pin Hung, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
  • Semiconductor device
    Patent number: 10770379
    Abstract: A semiconductor device 1 includes a first drain terminal 4, connected to a drain electrode of a first semiconductor chip, a first gate terminal 5, connected to a gate electrode of the first semiconductor chip, a second drain terminal 6, connected to a drain electrode of a second semiconductor chip, a second gate terminal 7, connected to a gate electrode of the second semiconductor chip, a common source terminal 8, connected to a source electrode of the first semiconductor chip and a source electrode of the second semiconductor chip, and a sealing resin 9, sealing the respective semiconductor chips and the respective terminals. The respective terminals have exposed surfaces (lower surfaces) 43, 53, 63, 73, and 83 substantially flush with an outer surface (lower surface) 9b of the sealing resin 9 and exposed from the outer surface 9b.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 8, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Yuki Kondo
  • Method of forming semiconductor structure having layer with re-entrant profile
    Patent number: 10755968
    Abstract: A method is provided. A sacrificial layer is formed over a semiconductor substrate. An etching process is performed to form an opening in the sacrificial layer. The etching process includes a first cycle and a second cycle performed after the first cycle, and each of the first cycle and the second cycle includes applying a passivation gas and an etchant gas over the sacrificial layer, and performing an ionized gas bombardment on the sacrificial layer after applying the passivation gas and the etchant gas over the sacrificial layer. The passivation gas is applied at a first flow rate in the first cycle and is applied at a second flow rate in the second cycle, and the first flow rate is higher than the second flow rate.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Shan Chen, Chan-Syun David Yang, Li-Te Lin, Pinyen Lin
  • Method thereof of package structure
    Patent number: 10756065
    Abstract: A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: August 25, 2020
    Assignee: Powertech Technology Inc.
    Inventors: Shang-Yu Chang Chien, Hung-Hsin Hsu, Nan-Chun Lin
  • Formation of conductive connection tracks in package mold body using electroless plating
    Patent number: 10741466
    Abstract: A first packaged semiconductor device is provided. The first packaged semiconductor device includes a first semiconductor die having a first terminal, a first electrically conductive lead that is electrically connected to the first terminal, and a first electrically insulating mold compound that encapsulates the first semiconductor die and exposes an end portion of the first lead at an outer surface of the first mold compound. A conductive track is formed in the outer surface of the first mold compound. Forming the conductive track includes activating a portion of the outer surface of the first mold compound for an electroless plating process, and performing the electroless plating process so as to form an electrically conductive material only within the activated portion of the outer surface of the first mold compound.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Cher Hau Danny Koh, Norliza Morban, Yong Chern Poh, Khay Chwan Saw, Si Hao Vincent Yeo
  • Fan-out semiconductor package
    Patent number: 10741461
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoung Joon Kim, Kyung Seob Oh, Kyoung Moo Harr
  • Stacked semiconductor device structure and method
    Patent number: 10741484
    Abstract: A method of forming stacked semiconductor device structure includes providing a first semiconductor device and a second semiconductor device. The first semiconductor device includes a recessed region bounded by sidewall portions and a conductive layer disposed adjoining at least portions of the recessed region. The method includes electrically connecting the second semiconductor device to the conductive layer within the recessed region such that at least a portion of the second semiconductor device is disposed within the recessed region.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: August 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Controlling back-end-of-line dimensions of semiconductor devices
    Patent number: 10727120
    Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming a metallization layer and depositing a hardmask layer over the metallization layer. A dielectric layer is deposited over the hardmask layer and an opening is formed in the dielectric layer to expose the hardmask layer. The exposed hardmask layer in the opening is etched to form an undercut beneath the dielectric layer. A metal shoulder is formed at the undercut, wherein the metal shoulder defines an aperture dimension used for forming a via opening extending to the metallization layer.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sean X Lin, Ruilong Xie, Guoxiang Ning, Lei Sun
  • Layer structure including diffusion barrier layer and method of manufacturing the same
    Patent number: 10727182
    Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunjae Song, Seunggeol Nam, Yeonchoo Cho, Seongjun Park, Hyeonjin Shin, Jaeho Lee
  • Semiconductor device and method of manufacture
    Patent number: 10727147
    Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
  • Embedding into printed circuit board with drilling
    Patent number: 10681819
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Semiconductor package
    Patent number: 10665535
    Abstract: A semiconductor package includes a semiconductor chip; a connection member having a first surface on which the semiconductor chip is disposed and a second surface opposing the first surface, an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip, a passivation layer on the second surface of the connection member; and an UBM layer partially embedded in the passivation layer, wherein the UBM layer includes an UBM via embedded in the passivation layer and connected to the redistribution layer of the connection member and an UBM pad connected to the UBM via and protruding from a surface of the passivation layer, and a width of a portion of the UBM via in contact with the UBM pad is narrower than a width of a portion of the UBM via in contact with the redistribution layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Ean Lee, Tae Sung Jeong, Young Gwan Ko, Suk Ho Lee, Jung Soo Byun
  • Oxidation resistant barrier metal process for semiconductor devices
    Patent number: 10665543
    Abstract: An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: May 26, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. West, Kezhakkedath R. Udayakumar, Eric H. Warninghoff, Alan G. Merriam, Rick A. Faust
  • Post-passivation interconnect structure and method of forming the same
    Patent number: 10651055
    Abstract: A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jen Lin, Tsung-Ding Wang, Chien-Hsun Lee
  • Semiconductor device with metal structure electrically connected to a conductive structure
    Patent number: 10651140
    Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor substrate that has a conductive structure, and forming a precursor auxiliary layer stack on a first section of the conductive structure. The precursor auxiliary layer stack has a precursor adhesion layer and a precursor barrier layer between the precursor adhesion layer and the conductive structure. The precursor adhesion layer contains a second metal. The method further includes forming, on the precursor auxiliary layer stack, a metal structure containing a first metal and forming, from portions of the precursor auxiliary layer stack an adhesive layer containing the first and second metals.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 12, 2020
    Assignee: Infineon Technologies AG
    Inventors: Manfred Schneegans, Franziska Haering, Hans-Joachim Schulze, Bernhard Weidgans
  • Process integration method to tune resistivity of nickel silicide
    Patent number: 10651043
    Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 12, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Minrui Yu, Mehul B. Naik
  • Heat-dissipating lid with reservoir structure and associated lidded flip chip package allowing for liquid thermal interfacing materials
    Patent number: 10643924
    Abstract: The disclosure describes a heat-dissipating object having a reservoir structure so that a reservoir system can be formed in an electronic device, allowing for a liquid TIM (thermal interface material) in the gap between the heat-dissipating object and the heat-generating object of the electronic device. The reservoir structure comprises a seal ring, a connecting hole and a reservoir which is a space for taking in a liquid material and releasing it again when needed. As a specific case of the heat-dissipating object and the electronic device, a lid having a reservoir structure and a lidded flip chip package based on the lid are particularly described in details of the embodiments of the present invention.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: May 5, 2020
    Inventor: Yuci Shen
  • Semiconductor package substrate and method for manufacturing same
    Patent number: 10643932
    Abstract: A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: May 5, 2020
    Assignee: Haesung DS CO., LTD.
    Inventors: In Seob Bae, Sung Il Kang
  • Semiconductor device having a structure for insulating layer under metal line
    Patent number: 10643926
    Abstract: A semiconductor device including a via plug formed on a substrate and a metal layer for interconnection formed at an end of the via plug, wherein an insulating structure is under the metal layer for interconnection and the insulating structure has a different layered structure according to a positional relationship with the metal layer for interconnection is disclosed.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Jun Choi, Doo Won Kwon, Kwan Sik Kim, Tae Young Song, Sung Hyun Yoon