Patents Examined by Nitin Parekh
  • Fan-out semiconductor package
    Patent number: 10985127
    Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: April 20, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong Ho Lee, Bong Ju Cho, Young Gwan Ko, Jin Su Kim, Shang Hoon Seo, Jeong Il Lee
  • Semiconductor package and manufacturing method thereof
    Patent number: 10985101
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes semiconductor dies, an encapsulant and a redistribution structure. The semiconductor dies are disposed side by side. Each semiconductor die has an active surface, a backside surface, and an inner side surface connecting the active surface and the backside surface. The encapsulant wraps the semiconductor dies and exposes the active surfaces of the semiconductor dies. The redistribution structure is disposed on the encapsulant and the active surfaces of the semiconductor dies. The inner side surfaces of most adjacent semiconductor dies face each other. The redistribution structure establishes single-ended connections between most adjacent semiconductor dies by crossing over the facing inner side surfaces of the most adjacent semiconductor dies.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Chi-Hui Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Kuo-Chung Yee, Chen-Hua Yu
  • Sensor
    Patent number: 10978597
    Abstract: A sensor includes a printed circuit board; at least one semiconductor chip arranged on the printed circuit board and includes a front-side contact, wherein the semiconductor chip is a radiation-detecting semiconductor chip; an embedding layer arranged on the printed circuit board and laterally adjoining the at least one semiconductor chip; and a contact layer connected to the front-side contact of the at least one semiconductor chip.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: April 13, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Dirk Becker, Matthias Sperl
  • Conductive feature formation and structure
    Patent number: 10971396
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back. After etching back the portion of the barrier layer, an upper portion of the barrier layer along the sidewall is smoothed. A conductive material is formed along the barrier layer and over the smoothed upper portion of the barrier layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu Shih Wang, Chun-I Tsai, Shian Wei Mao, Ken-Yu Chang, Ming-Hsing Tsai, Wei-Jung Lin
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10971483
    Abstract: A semiconductor package and method of manufacturing the same are provided. A semiconductor package includes an interconnect layer comprising first conductive pads configured as bond pads and second conductive pads configured as test pads, a plurality of conductive pillars over the interconnect layer, and a first semiconductor die bonded to the interconnect layer through the first conductive pads. The semiconductor package also includes an integrated passive device bonded to the interconnect layer through the first conductive pads, wherein the integrated passive device and the first semiconductor die are disposed on a same side of the interconnect layer, a second semiconductor die electrically coupled to the conductive pillars, and an encapsulating material surrounding the first semiconductor die, the integrated passive device and the conductive pillars.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Puu Jeng, Jui-Pin Hung, Feng-Cheng Hsu
  • Maskless air gap to prevent via punch through
    Patent number: 10971394
    Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Todd R. Younkin, Eungnak Han, Jasmeet S. Chawla, Marie Krysak, Hui Jae Yoo, Tristan A. Tronic
  • Semiconductor device and method for manufacturing the same
    Patent number: 10964681
    Abstract: A semiconductor device includes a substrate, first and second semiconductor chips, an adhesion layer, and a resin layer. The first and second semiconductor chips are provided on a surface of the substrate. The second semiconductor chip includes, on a side thereof facing the substrate, a first region and a second region that is recessed from the first region and is above at least part of the first semiconductor chip or at least part of a wire that electrically connects the first semiconductor chip and the substrate. The adhesion layer is provided at least between the first region of the second semiconductor chip and the substrate. The resin layer is on the surface of the substrate and enclosing the first and second semiconductor chips.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Eigo Matsuura
  • Package and light emitting device
    Patent number: 10964637
    Abstract: A package includes a first lead and a second lead. The first lead includes a first part and a second part connected to the first part. The second lead includes a third part and a fourth part connected to the third part. A molded body having a front surface and rear surface opposite to the front surface. The first part has a first terminal exposed from the rear surface. The first terminal is provided within an outer peripheral edge of the rear surface. The third part has a second terminal exposed from the rear surface. The second terminal is provided within the outer peripheral edge. The first lead or the second lead has a heat releasing terminal exposed from the rear surface. The heat releasing terminal is disposed between the first terminal and the second terminal to be spaced apart from the first terminal and the second terminal.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 30, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Yuki Shiota
  • EMI shielding structure in InFO package
    Patent number: 10950556
    Abstract: A method includes forming a metal post over a first dielectric layer, attaching a second dielectric layer over the first dielectric layer, encapsulating a device die, the second dielectric layer, a shielding structure, and the metal post in an encapsulating material, planarizing the encapsulating material to reveal the device die, the shielding structure, and the metal post, and forming an antenna electrically coupling to the device die. The antenna has a portion vertically aligned to a portion of the device die.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chen-Hua Yu, Ching-Feng Yang, Meng-Tse Chen
  • Semiconductor package and method of fabricating semiconductor package
    Patent number: 10937688
    Abstract: A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
  • Semiconductor package with in-package compartmental shielding and improved heat-dissipation performance
    Patent number: 10923435
    Abstract: A semiconductor package includes a substrate having at least one semiconductor chip on a top surface of the substrate; a ground ring, on the top surface of the substrate, surrounding the at least one semiconductor chip; a metal-post reinforced glue wall disposed on the ground ring, surrounding the at least one semiconductor chip; a molding compound surrounding the at least one semiconductor chip, wherein a rear surface of the at least one semiconductor chip is flush with an upper surface of the molding compound; a conductive layer disposed on the molding compound and in direct contact with the rear surface of the semiconductor chip and the metal-post reinforced glue wall; a solder layer disposed on the conductive layer; and a heat sink disposed on the solder layer.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: February 16, 2021
    Inventors: Shiann-Tsong Tsai, Hsien-Chou Tsai, Hsien-Wei Tsai, Yen-Mei Tsai Huang
  • Semiconductor device and a method of manufacturing thereof
    Patent number: 10910335
    Abstract: A light-emitting module includes a common carrier; a plurality of semiconductor devices formed on the common carrier, and each of the plurality of semiconductor devices including three semiconductor dies; a carrier including a connecting surface; a third bonding pad and a fourth bonding pad formed on the connecting surface; and a connecting layer. One of the three semiconductor dies includes a stacking structure; a first bonding pad; and a second bonding pad with a shortest distance less than 150 microns between the first bonding pad. The connecting layer includes a first conductive part including a first conductive material having a first shape; and a blocking part covering the first conductive part and including a second conductive material having a second shape with a diameter in a cross-sectional view. The first shape has a height greater than the diameter.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: February 2, 2021
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-An Liao, Shau-Yi Chen, Ming-Chi Hsu, Chun-Hung Liu, Min-Hsun Hsieh
  • Packaging structure and packaging method for antenna
    Patent number: 10886594
    Abstract: The present disclosure provides a packaging structure and a packaging method for an antenna. The packaging structure comprises a redistribution layer, having a first surface and an opposite second surface; a first metal joint pin, formed on the second surface of the redistribution layer; a first packaging layer, disposed on the redistribution layer covering the first metal joint pin; a first antenna metal layer, patterned on the first packaging layer, and a portion of the first antenna metal layer electrically connects with the first metal joint pin; a second metal joint pin, formed on the first antenna metal layer; a second packaging layer, disposed on the first antenna metal layer covering the second metal joint pin; a second antenna metal layer, formed on the second packaging layer; and a metal bump and an antenna circuit chip, bonded to the first surface of the redistribution layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: January 5, 2021
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin
  • Package structure and fabrication methods
    Patent number: 10886232
    Abstract: The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor package. In one embodiment, a glass or silicon substrate is structured by micro-blasting or laser ablation to form structures for formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor package with embedded dies therein.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: January 5, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Han-Wen Chen, Steven Verhaverbeke, Giback Park, Giorgio Cellere, Diego Tonini, Vincent DiCaprio, Kyuil Cho
  • Semiconductor device and method of manufacture
    Patent number: 10879183
    Abstract: A device includes a redistribution structure, a semiconductor device on the redistribution structure, a top package over the semiconductor device, the top package including a second semiconductor device, a molding compound interposed between the redistribution structure and the top package, a set of through vias between and electrically connecting the top package to the redistribution structure, and an interconnect structure disposed within the molding compound and electrically connecting the top package to the redistribution structure, the interconnect structure including a substrate and a passive device formed in the substrate, wherein the interconnect structure is free of active devices.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu
  • Method of manufacturing package structure
    Patent number: 10879147
    Abstract: A method of manufacturing a package structure includes the following processes. A carrier is provided. An adhesive layer is formed on the carrier. A die is attached to the carrier through the adhesive layer. An encapsulant is formed over the carrier to laterally encapsulate the die. A polymer material is formed over the carrier along a surface of the adhesive layer, a surface of the encapsulant and a top surface of the die. A first portion of the polymer material directly on an edge of the carrier has a first thickness larger than a second thickness of a second portion of the polymer material directly on the top surface of the die. A redistribution layer is formed to penetrate through the second portion of the polymer layer and electrically connect to the die.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Hung-Jui Kuo, Yu-Hsiang Hu
  • Electronic device and method of manufacture therefor
    Patent number: 10879145
    Abstract: An electronic device includes electronic components, a molded resin element wherein the electronic components are embedded and secured, and a heat transfer layer; the heat transfer layer has a higher thermal conductivity than the molded resin element. The heat transfer layer is in contact with portions of the electronic components other than an electrode pad and a terminal. This prevents increases in the cost of manufacturing the electronic device and the allows the electronic device to be thinner.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: December 29, 2020
    Assignee: OMRON Corporation
    Inventor: Wakahiro Kawai
  • Die stack structure and method of fabricating the same
    Patent number: 10867963
    Abstract: A die stack structure includes a first die, a dielectric material layer, a first bonding dielectric layer and a second die. The first die has an active surface and a rear surface opposite to the active surface. The first die includes a through-substrate via (TSV) therein. The TSV protrudes from the rear surface of the first die. The dielectric material layer surrounds and wraps around the first die. The first bonding dielectric layer is disposed on a top surface of the dielectric material layer and the rear surface of the first die and covers the TSV, wherein the TSV penetrates through the first bonding dielectric layer. The second die is disposed on the first die and has an active surface and a rear surface opposite to the active surface. The second die has a second bonding dielectric layer and a conductive feature disposed in the second bonding dielectric layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Chien-Ming Chiu, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • 3D package structure and methods of forming same
    Patent number: 10861827
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Antenna package structure and antenna packaging method
    Patent number: 10854951
    Abstract: The present disclosure provides an antenna package structure and an antenna packaging method for a semiconductor chip. The package structure includes an antenna circuit chip, a first rewiring layer, an antenna structure, a second metal connecting column, a second packaging layer, a second antenna metal layer, and a second metal bump. The antenna circuit chip, the antenna structure, and the second antenna metal layer are interconnected by using two rewiring layers and two layers of metal connecting columns.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: December 1, 2020
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Yenheng Chen, Chengchung Lin, Chengtar Wu, Jangshen Lin