Abstract: An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, which at least includes discrete conducting layers in the semiconductor substrate; forming discretely arranged supporting structures on the semiconductor substrate, capacitor openings being included between the supporting structures; forming lower electrodes on sidewalls of the supporting structures, the lower electrodes being electrically connected with the conducting layers; forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and forming an upper electrode covering the capacitor dielectric layer, to form capacitor structures.

Abstract: A packaged module and a metal plate. The packaged module may include a bearing structure, at least one metal strip, a circuit element, and a magnetic material. Further, a first surface of the bearing structure may bear the circuit element; two ends of each of the at least one metal strip may be coupled to the bearing structure, and a part of each metal strip other than the two ends is spaced apart from the bearing structure; and the magnetic material may cover a surface of a winding functional region of the at least one metal strip, where the winding functional region may be a part or all of the metal strip to which the winding functional region belongs. The foregoing solution helps simplify a packaging process and reduce losses and manufacturing costs of the packaged module.

Abstract: Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.

Abstract: A metal-insulator-metal capacitor includes a first electrode disposed in a first region of an upper surface of a substrate, a second electrode covering the first electrode and extending to a second region surrounding an outer periphery of the first region, a third electrode covering the second electrode and extending to a third region surrounding an outer periphery of the second region, a first dielectric layer disposed between the first electrode and the second electrode to cover an upper surface and a side surface of the first electrode and extending to the second region, and a second dielectric layer disposed between the second electrode and the third electrode to cover an upper surface and a side surface of the second electrode and extending to the third region and in contact with the first dielectric layer.

Abstract: A light-emitting device is described that includes a plurality of partially drivable light sources, and a color conversion component configured to convert at least part of incident light from at least part of the light sources and emit outgoing light falling in a different wavelength region from the incident light, where the color conversion component includes a pyrromethene derivative.

Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

Abstract: A light-emitting device comprises a substrate; a first light-emitting unit and a second light-emitting unit formed on the substrate, each of the first light-emitting unit and the second light-emitting unit comprises a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer, wherein the first light-emitting unit comprises a first semiconductor mesa and a first surrounding part surrounding the first semiconductor mesa, and the second light-emitting unit comprises a second semiconductor mesa and a second surrounding part surrounding the second semiconductor mesa; a trench formed between the first light-emitting unit and the second light-emitting unit and exposing the substrate; a first insulating layer comprising a first opening on the first surrounding part and a second opening on the second semiconductor layer of the second light-emitting unit; and a connecting electrode comprising a first connecting part on the first

Abstract: A method for manufacturing a device comprising a membrane extending over a useful cavity, the method comprising: providing a generic structure comprising a surface layer extending in a main plane and arranged on a first face of a support substrate, the support substrate comprising elementary cavities opening under the surface layer and partitions delimiting each elementary cavity, the partitions having top surfaces that form all or part of the first face of the support substrate; defining a group of adjacent elementary cavities, such that a contour of the group of elementary cavities corresponds, in the main plane, to a contour of the useful cavity; and removing the partitions situated within the contour of the group of elementary cavities, in order to form the useful cavity, and to free the surface layer arranged above the useful cavity and forming the membrane.

Abstract: An electronic device includes a display panel, a first optical part, and a second optical part including a diffraction optical element having a diffraction grating. The display panel include a first display area for displaying a first image having a first color, a second display area disposed adjacent to the first display area to display a second image having a second color different from the first color, and a third display area disposed adjacent to the second display area to display a third image having a third color different from the first color and the second color.

Abstract: A semiconductor package assembly includes a semiconductor package that includes a semiconductor chip bonded to a substrate. The assembly also includes a plurality of passive devices mounted on a bottom surface of the substrate opposite the semiconductor chip, the plurality of passive devices including a plurality of operable passive devices and a plurality of standoff passive devices, wherein a height of each of the plurality of standoff passive devices is greater than a height of any of the plurality of operable passive devices. The assembly also includes a plurality of solder structures attached to the bottom surface of the substrate. When mounted on a circuit board, the standoff passive devices prevent solder bridging.

Abstract: Described herein is an electronic component that may include a substrate, wherein the substrate may include at least two electrodes, wherein the at least two electrodes are each spaced apart from each other on and/or within the substrate. When the electronic component is in a first operating state, an electrolytic material may be disposed at least in a spatial region between the at least two electrodes, wherein the electrolytic material comprises at least one polymerizable material. When the electronic device is in a second operating state, at least one electrical connection may be made between the at least two electrodes, wherein the at least one electrical connection comprises an electrically conductive polymer. The electrically conductive polymer may comprise one or more fiber structures, wherein the one or more fiber structures are in physical contact with the at least two electrodes.

Abstract: A first electrode (110) has optical transparency, and a second electrode (130) has light reflectivity. An organic layer (120) is located between the first electrode (110) and the second electrode (130). Light-transmitting regions (a second region (104) and a third region (106)) are located between a plurality of light-emitting units (140). An insulating film (150) defines the light-emitting units (140) and includes tapers (152, 154). A sealing member (170) covers the light-emitting units (140) and the insulating film (150). A low reflection film (190) is located on the side opposite to a substrate (100) with the second electrode (130) therebetween. The low reflection film (190) covers at least one portion of the tapers (152 and 154).

Abstract: Examples of a substrate processing apparatus includes a chamber, an upper cover provided inside the chamber, an electrostatic chuck which includes an annular portion of a dielectric body and an embedded electrode embedded into the annular portion, the electrostatic chuck being provided inside the chamber, and a plasma unit configured to generate plasma in a region below the upper cover and the electrostatic chuck, wherein the annular portion includes an annular first upper surface located immediately below the upper cover, and a second upper surface located immediately below the upper cover and surrounding the first upper surface, the second upper surface having a height higher than a height of the first upper surface.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a first metal nitride structure, a second metal nitride structure spaced from the first metal nitride structure, and a metal structure disposed between the first metal nitride structure and the second metal nitride structure. A first dielectric structure is disposed over the substrate and the resistor.

Abstract: A method for forming a double-sided capacitor structure includes: providing a base, the base including a substrate, a plurality of capacitor contacts located in the substrate, a stack structure located on a surface of the substrate and a plurality of capacitor holes running through the stack structure and exposing the capacitor contacts, the stack structure including sacrificial layers and support layers which are stacked alternately; successively forming a first electrode layer, a first dielectric layer and a second electrode layer on inner walls of the capacitor holes; forming a first conductive filling layer in the capacitor holes; forming an auxiliary layer for sealing the capacitor holes; removing a part of the auxiliary layers and several of the support layers and the sacrificial layers to expose the first electrode layer; and, forming a second dielectric layer and a third electrode layer.

Abstract: A method for fabricating a semiconductor device is described that includes forming a base layer over a top layer of a substrate, the base layer includes a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm; forming a photoresist layer over the base layer, the photoresist including a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.

Abstract: A substrate processing apparatus that includes a substrate holder, a cup member, an elevating mechanism, a first nozzle, and a camera. The substrate holder holds a substrate and rotates the substrate. The cup member surrounds the outer circumference of the substrate holder. The elevating mechanism moves up the cup member so that the upper end portion of the cup member is located at the upper end position higher than the substrate held by the substrate holder. The first nozzle has a discharge port at a position lower than the upper end position, and discharges first processing liquid from the discharge port to an end portion of the substrate. The camera images an imaging region that includes the first processing liquid discharged from the discharge port of the first nozzle and is viewed from an imaging position above the substrate.

Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Abstract: An embodiment of the disclosure provides a package device including a redistribution layer, an integrated passive device layer, a first port, and a second port. The integrated passive device layer contacts the redistribution layer. The integrated passive device layer has at least one capacitor. The at least one capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is provided opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance.