Patents Examined by Omar F Mojaddedi
  • Patent number: 11515434
    Abstract: A semiconductor device includes a substrate and a plurality of source/drain (S/D) regions in the substrate, wherein each of the plurality of S/D regions includes a first dopant having a first dopant type, and the each of the plurality of S/D regions are electrically coupled together. The semiconductor device further includes a gate stack over the substrate. The semiconductor device further includes a channel region in the substrate, wherein the channel region is below the gate stack and between adjacent S/D regions of the plurality of S/D regions, the channel region includes a second dopant having the first dopant type, and a concentration of the second dopant in the channel region is less than a concentration of the first dopant in each of the plurality of S/D regions.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Lin Liu, Jaw-Juinn Horng
  • Patent number: 11515396
    Abstract: Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 ?. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Albert Liao, Manzar Siddik
  • Patent number: 11508646
    Abstract: A semiconductor device comprises; a lead frame having leads and a die pad; a printed circuit board including an electrode for the connection of each of the leads and the die pad, a wiring pattern, and an opening exposing a part of a surface of the die pad; the semiconductor element for processing a high frequency signal, mounted on a surface of a metal block bonded to the surface of the die pad exposed through the opening, and connected to the wiring pattern with a metal wire; electronic components connected to the wiring pattern and mounted on a surface of the printed circuit board; and a sealing resin to seal the printed circuit board, the semiconductor element, the electronic components, and the metal wire so as to expose rear surfaces of the leads and the die pad.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 22, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Miyawaki
  • Patent number: 11508654
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 22, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Luisa Lin, Mohan Dunga, Venkatesh P. Ramachandra, Peter Rabkin, Masaaki Higashitani
  • Patent number: 11502265
    Abstract: A quantum dot white light-emitting diode includes a cathode, an anode, and a light-emitting layer disposed therebetween. The light-emitting layer includes: a blue fluorescent organic layer, a spacer layer, and a quantum dot light-emitting layer. The blue fluorescent organic layer is disposed near the cathode side, the quantum dot light-emitting layer is disposed near the anode side, and the spacer layer is disposed between the blue fluorescent organic layer and the quantum dot light-emitting layer. A material of the quantum dot light-emitting layer contains quantum dots, a material of the blue fluorescent organic layer contains a blue fluorescent organic material, and a material of the spacer layer contains a spacer material. A triplet exciton energy of the spacer material is greater than a triplet exciton energy of the blue fluorescent organic material, and a triplet exciton energy of the spacer material is greater than a quantum dot exciton energy.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: November 15, 2022
    Assignee: TCL TECHNOLOGY GROUP CORPORATION
    Inventors: Liang Su, Xiangwei Xie
  • Patent number: 11502064
    Abstract: Described is a power semiconductor module that includes: a frame made of an electrically insulative material; a first substrate seated in the frame; a plurality of power semiconductor dies attached to the first substrate; a plurality of signal pins attached to the first substrate and electrically connected to the power semiconductor dies; a busbar extending from the first substrate through a side face of the frame; a current sensor module seated in a receptacle of the frame in sensing proximity of the busbar, the current sensor module including a current sensor attached to a circuit board; and a potting material fixing the current sensor module to the frame such that no air gap is present between the current sensor and the busbar. The potting material contacts the frame and the current sensor. Methods of producing the power semiconductor module are also described.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: November 15, 2022
    Assignee: Infineon Technologies AG
    Inventors: Tomas Manuel Reiter, Christoph Koch, Mark Nils Muenzer
  • Patent number: 11495684
    Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Han Chu, Nai-Chia Chen, Ping-Jung Huang, Tsung-Min Chuo, Jui-Ming Shih, Bi-Ming Yen
  • Patent number: 11495737
    Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 8, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Shih-Wei Su, Bin-Siang Tsai, Ting-An Chien
  • Patent number: 11495617
    Abstract: Device, systems, and structures include a stack of vertically-alternating tiers of materials arranged in one or more decks of tiers. A channel opening, in which a channel pillar may be formed, extends through the stack. The pillar includes a “shoulder portion” extending laterally into an “undercut portion” of the channel opening, which undercut portion is defined along at least a lower tier of at least one of the decks of the stack.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Nancy M. Lomeli, Justin B. Dorhout, Damir Fazil
  • Patent number: 11489133
    Abstract: A novel light-emitting device is provided. A light-emitting device with high emission efficiency is provided. A light-emitting device with along lifetime is provided. A light-emitting device with low driving voltage is provided. The light-emitting device includes an anode, a cathode, and an EL layer between the anode and the cathode. The EL layer includes a hole-injection layer, a light-emitting layer, and an electron-transport layer. The hole-injection layer is positioned between the anode and the light-emitting layer. The electron-transport layer is positioned between the light-emitting layer and the cathode. The hole-injection layer contains a first substance and a second substance. The first substance is an organic compound which has a hole-transport property and a HOMO level higher than or equal to ?5.7 eV and lower than or equal to ?5.4 eV. The second substance exhibits an electron-accepting property with respect to the first substance.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: November 1, 2022
    Inventors: Satoshi Seo, Hiromi Seo, Kunihiko Suzuki, Kanta Abe, Yuji Iwaki, Naoaki Hashimoto, Tsunenori Suzuki
  • Patent number: 11476152
    Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 18, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11469168
    Abstract: A capacitor includes at least one multi-wing structure; a laminated structure, where the laminated structure clads the at least one multi-wing structure and includes at least one dielectric layer and a plurality of conductive layers, and the at least one dielectric layer and the plurality of conductive layers form a structure that a conductive layer and a dielectric layer are adjacent to each other; at least one first external electrode, where the first external electrode is electrically connected to some conductive layer(s) in the plurality of conductive layers; at least one second external electrode, wherein the second external electrode is electrically connected to the other conductive layer(s) in the plurality of conductive layers, and a conductive layer in the laminated structure adjacent to each conductive layer in the some conductive layer(s) includes at least one conductive layer in the other conductive layer(s).
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: October 11, 2022
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Bin Lu, Jian Shen
  • Patent number: 11459231
    Abstract: The present disclosure provides a microelectronic isolation system comprising a base, vibration isolator, primary sensor, and microprocessor. The base supports the vibration isolator, the primary sensor, and the microprocessor. The vibration isolator has a platform, isolation material, and at least one isolation sensor. The isolation material dampens an overall vibrational frequency experienced by the microelectronic isolation system. The isolation sensor measures a displacement. The displacement is a measurement of a displacement of the platform with respect to the base. The primary sensor measures a primary sensor response, which is received by the microprocessor to calculate a plurality of responses. The plurality of responses of the microprocessor being one or a combination of a measured compensation response, an inertial response, and a restored primary sensor response.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: October 4, 2022
    Assignee: United States Government as represented by the Secretary of the Army
    Inventor: Clinton Blankenship
  • Patent number: 11460499
    Abstract: An integrated circuit package having an electronic interposer comprising an upper section, a lower section and a middle section, a die side integrated circuit device electrically attached to the upper section of the electronic interposer, a die side heat dissipation device thermally contacting the die side integrated circuit device, a land side integrated circuit device electrically attached to the lower section of the electronic interposer, and a land side heat dissipation device thermally contacting the at least one die side integrated circuit device. The upper section and the lower section may each have between two and four layers and the middle section may be formed between the upper section and the lower section, and comprises up to eight layers, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Aleksandar Aleksov, Veronica Strong, Brandon Rawlings, Johanna Swan, Shawna Liff
  • Patent number: 11462610
    Abstract: Capacitor forming methods may include sequentially forming a first mold layer, a first support material layer, and a second mold layer on a substrate, forming a mask pattern on the second mold layer, forming a recess in the second mold layer, the first support material layer, and the first mold layer using the mask pattern as a mask, forming a lower electrode in the recess, removing the mask pattern by a dry cleaning process, reducing a width of an upper portion of the lower electrode, removing the first mold layer, forming a dielectric layer on a surface of the lower electrode, and forming an upper electrode on the dielectric layer.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoonyoung Choi, Byunghyun Lee, Byeongjoo Ku, Seungjin Kim, Sangjae Park, Jinwoo Bae, Hangeol Lee, Bowo Choi, Hyunsil Hong
  • Patent number: 11462609
    Abstract: A capacitor includes: at least one multi-wing structure including N axes and M wings, where the N axes extend along a first direction, and the M wings are a convex structure formed by extending from side walls of the N axes toward a direction perpendicular to the first direction, a first wing of the M wings and the N axes are formed of a first conductive material, and other wings are formed of a second conductive material; a conductive structure cladding the multi-wing structure; a dielectric layer disposed between the multi-wing structure and the conductive structure to isolate the multi-wing structure from the conductive structure; a first external electrode electrically connected to some or all multi-wing structures; and a second external electrode electrically connected to the conductive structure.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: October 4, 2022
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Bin Lu, Jian Shen
  • Patent number: 11450659
    Abstract: A semiconductor device including a decoupling capacitor disposed between adjacent device source-drain regions, the decoupling capacitor comprising an outer metal liner, a dielectric disposed adjacent to the outer metal liner, and an inner metal liner disposed adjacent to the dielectric, a single diffusion break isolation region disposed between the adjacent device source-drain regions. The outer metal liner is disposed in electrical contact with the adjacent device source-drain regions.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: September 20, 2022
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Ruilong Xie, Jingyun Zhang, Lan Yu
  • Patent number: 11441964
    Abstract: A micromechanical pressure sensor device is equipped with a sensor substrate including a front side and a rear side. The device includes a pressure sensor unit suspended in the sensor substrate, a first cavity above the pressure sensor unit, which is exposed toward the front side via one or multiple access openings, one or multiple stress relief trenches, which laterally enclose the pressure sensor unit and form a fluidic connection from the rear side to the first cavity, and a circuit substrate, on which the rear side of the sensor substrate is bonded. A second cavity, which is in fluidic connection with the stress relief trenches, is formed below the pressure sensor unit in the circuit substrate. At least one channel is provided in a periphery of the pressure sensor unit, which is in fluidic connection with the second cavity and is exposed to the outside.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: September 13, 2022
    Assignee: Robert Bosch GmbH
    Inventors: Volkmar Senz, Arne Dannenberg, Jochen Franz
  • Patent number: 11444016
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 13, 2022
    Assignee: SanDisk Technologes LLC
    Inventors: Luisa Lin, Mohan Dunga, Venkatesh P. Ramachandra, Peter Rabkin, Masaaki Higashitani
  • Patent number: 11437305
    Abstract: A semiconductor module includes: semiconductor devices; a resin mold that integrally seals the semiconductor devices; and external terminals that are disposed at a lateral side of the resin mold along a direction perpendicular to a thickness direction of the semiconductor devices. Each semiconductor device includes an insulated gate semiconductor device having a gate electrode, a first electrode, and a second electrode. In the insulated gate semiconductor device, carriers move from the first electrode to the second electrode through a channel provided by a voltage applied to the gate electrode. The external terminals include: a gate terminal electrically connected to the gate electrode; a first terminal electrically connected to the first electrode; and a second terminal electrically connected to the second electrode. The gate terminal and the second terminal, which are electrically connected to an identical semiconductor device, are not adjacent to each other.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: September 6, 2022
    Assignee: DENSO CORPORATION
    Inventors: Shuhei Miyachi, Takaharu Kozawa, Toshihiro Fujita