Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: Methods and systems for implementing artificial intelligence enabled preparation end-pointing are disclosed. An example method at least includes obtaining an image of a surface of a sample, the sample including a plurality of features, analyzing the image to determine whether an end point has been reached, the end point based on a feature of interest out of the plurality of features observable in the image, and based on the end point not being reached, removing a layer of material from the surface of the sample.

Abstract: The present application discloses a semiconductor device with a horizontally arranged capacitor. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.

Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

Abstract: A variety of applications can include apparatus having a memory device with an array of vertical strings of memory cells for the memory device with data lines coupled to the vertical strings, where the data lines have been formed by a metal liner deposition process. In the metal liner deposition, a metal can be formed on a patterned dielectric region. The metal liner deposition process allows for construction of the height of the data lines to be well controlled with selection of a thickness for the dielectric region used in forming the metal liner. Use of a metal liner deposition provides a controlled mechanism to reduce data line capacitance by being able to select liner thickness in forming the data lines. The use of the dielectric region with the metal liner deposition can allow the fabrication of the data lines to avoid pitch double or pitch quad processes.

Abstract: The present invention discloses a method for preparing a semiconductor sample for failure analysis, which is characterized by using an adhesive layer comprising a non-volatile and non-liquid adhesive material with higher adhesion to the dielectric materials and lower adhesion to the metallic contact materials to selectively remove part of the dielectric materials in a large area with high uniformity, but completely remain the metallic contact materials, and not chemically react with the semiconductor specimens or even damage to the structures of interest to be analyzed, and different adhesive materials can be selected as the adhesive layer to control the adhesion to the dielectric layer, thereby the removed thickness of the dielectric layer can be controlled to provide a semiconductor specimen for failure analysis.

Abstract: Resistive switching devices that contain lithium, including resistive switching devices containing a lithium titanate, and associated systems and methods are generally described. In some cases, the resistive switching device contains a lithium titanate-containing domain, a first electrode, and a second electrode. In some cases, the application of an electrical potential to the resistive switching device causes a change in resistance state of the lithium titanate-containing domain. The resistive switching devices described herein may be useful as memristors, and in applications that include Resistive-random access memory and neuromorphic computing.

Abstract: A reflective mask blank for EUV lithography includes: a substrate; a multilayer reflective film for reflecting EUV light; and a phase shift film for shifting a phase of EUV light, the multilayer reflective film and the phase shift film formed on or above the substrate in this order. The phase shift film includes a layer 1 including ruthenium (Ru) and at least one selected from the group consisting of oxygen (O) and nitrogen (N). Among diffraction peaks derived from the phase shift film observed at 2?: from 20° to 50° by out-of-plane XRD method, a peak having the highest intensity has a half value width FWHM of 1.0° or more.

Abstract: A circuit module includes a first wiring substrate having a first main surface and a plurality of first components mounted on the first main surface. The plurality of first components includes a multilayer component formed as a single chip by being sealed using resin members. The multilayer component includes a second wiring substrate having a second main surface and a third main surface that face each other, a second component mounted on the second main surface, and a third component mounted on the third main surface.

Abstract: A method for making a quantum device including: forming, over a semiconductor layer, a graphoepitaxy guide forming a cavity with a lateral dimension that is a multiple of a period of self-assembly of a di-block copolymer into lamellas; first deposition of the copolymer in the cavity; first self-assembly of the copolymer, forming a first alternating arrangement of first lamellas and of second lamellas; removal of the first lamellas; implantation of dopants in portions of the semiconductor layer previously covered with the first lamellas; removal of the second lamellas; second deposition of the copolymer in the cavity, over a gate material; second self-assembly of the copolymer, forming a second alternating arrangement of first and second lamellas; removal of the second lamellas; etching of portions of the gate material previously covered with the second lamellas.

Abstract: Image sensors are provided. The image sensors may include a substrate including first, second, third and fourth regions, a first photoelectric conversion element in the first region, a second photoelectric conversion element in the second region, a third photoelectric conversion element in the third region, a fourth photoelectric conversion element in the fourth region, a first microlens at least partially overlapping both the first and second photoelectric conversion elements, and a second microlens at least partially overlapping both the third and fourth photoelectric conversion elements. The image sensors may also include a floating diffusion region and first, second and third pixel transistors configured to perform different functions from each other. Each of the first, second and third pixel transistors may be disposed in at least one of first, second, third and fourth pixel regions. The first pixel transistor may include multiple first pixel transistors.

Abstract: A substrate for semiconductor module includes a plurality of insulating layers sequentially stacked on one another, N signal lines transmitting N signals respectively, the N signal lines having N vias that at least partially penetrate through the plurality of insulating layers and are arranged in an N-sided polygon shape in a plan view, and a capacitor element configured to provide capacitive coupling between the N signal lines, the capacitor element having a first coupling element that provides capacitive coupling between first and second vias adjacent to each other among the N vias and a second coupling element that provides capacitive coupling between third and fourth vias that are not adjacent to each other among the N vias.

Abstract: A constraint for a sensor assembly includes a silicon wafer and a flexible structure. The silicon wafer has a first side, a second side opposite to the first side, and a passageway extending through the silicon wafer from the first side to the second side. The first side is a continuous planar surface except for the passageway. The flexible structure extends from the second side.

Abstract: A semiconductor package comprises a lead frame, a low side metal-oxide-semiconductor field-effect transistor (MOSFET), an E-fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an E-fuse IC, and a molding encapsulation. A buck converter comprises a smart power stage (SPS) network and an E-fuse solution network. The SPS network comprises a high side switch, a low side switch, and a gate driver. A drain of the low side switch is coupled to a source of the high side switch via a switch node. The gate driver is coupled to a gate of the high side switch and a gate of the low side switch. The E-fuse solution network comprises a sense resistor, an E-fuse switch, an E-fuse integrated circuit (IC), and an SD circuit.

Abstract: A semiconductor device includes a substrate and at least one capacitor element on each of opposite surfaces of the substrate. The at least one capacitor element includes a first electrode with a first pad and first terminals connected to the first pad, wherein the first terminals extend away from the substrate, and a second electrode with a second pad and second terminals connected to the second pad, wherein the second terminals extend toward the substrate, wherein the first terminals and the second terminals are staggered and separated by an interlayer dielectric layer.

Abstract: A preparation method for a solar cell back electrode and an application thereof are provided. The method comprises setting a back electrode barrier layer and using back-side silver paste in coordination. The back electrode barrier layer comprises the following components: 20 to 80 parts by weight of metal nitride powder, nitrogen-silicon compound powder, oxide powder or low-melting-point metal powder in total; 0.5 to 5 parts by weight of lead-free glass powder; 10 to 40 parts by weight of organic carrier; and 0.1 to 1 part by weight of organic additives. The back-side silver paste comprises the following components: 5 to 60 parts by weight of hollow spherical silver powder; 5 to 30 parts by weight of flaky silver powder; 0.5 to 5 parts by weight of lead-free glass powder; 10 to 50 part by weight of organic binder; and 0.1 to 1 part by weight of organic additives.

Abstract: Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.

Abstract: A capacitor structure implemented as a layered structure including a plurality of alternating dielectric and metallization layers, and a method of manufacturing such capacitor structure. The capacitor structure including at least one lateral parallel plate capacitor part (LPP part) including two first electrodes on two different layers separated by dielectric material of a plurality of the alternating layers, and at least one vertical parallel plate capacitor part (VPP part) including two second electrodes each including a plurality of superimposed slabs or bars arranged on a plurality of the metallization layers. The at least one LPP part is electrically coupled with the at least one VPP part to form the capacitor structure. A variation in capacitance value of the at least one LPP part due to a variation of thickness of dielectric material is at least partially compensated by an opposite variation in capacitance value of the at least one VPP part.

Abstract: Image quality is improved. In an image pickup element, an interval between adjacent light receiving elements on a light receiving surface is changed depending on a position on the light receiving surface. Further, the image pickup element is manufactured by a method of manufacturing the image pickup element including layering photodiodes by repeatedly performing a silicon epitaxial process and an ion injection process. Further, the image pickup element is manufactured by the method of manufacturing the image pickup element including changing an interval between the photodiodes adjacent on the light receiving surface of the image pickup element in each layer depending on a position on the light receiving surface in addition to the layering thereof.

Abstract: A manufacturing method of a capacitive structure includes: providing a semiconductor base; forming a first mask layer on the semiconductor base, the first mask layer having a plurality of first round hole patterns distributed uniformly; forming first openings distributed uniformly on the semiconductor base by etching based on the first round hole patterns; forming a second mask layer on one side, away from the semiconductor base, of the first openings, and forming a plurality of second patterns on the second mask layer; forming second openings distributed uniformly on the semiconductor base by etching based on the second patterns; and etching the first openings and the second openings to form capacitive holes, and depositing a lower electrode layer, a dielectric layer and an upper electrode layer within the capacitive holes to form the capacitive structure.