Abstract: A method for fabricating a semiconductor device is described that includes forming a base layer over a top layer of a substrate, the base layer includes a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm; forming a photoresist layer over the base layer, the photoresist including a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.

Abstract: A substrate processing apparatus that includes a substrate holder, a cup member, an elevating mechanism, a first nozzle, and a camera. The substrate holder holds a substrate and rotates the substrate. The cup member surrounds the outer circumference of the substrate holder. The elevating mechanism moves up the cup member so that the upper end portion of the cup member is located at the upper end position higher than the substrate held by the substrate holder. The first nozzle has a discharge port at a position lower than the upper end position, and discharges first processing liquid from the discharge port to an end portion of the substrate. The camera images an imaging region that includes the first processing liquid discharged from the discharge port of the first nozzle and is viewed from an imaging position above the substrate.

Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Abstract: An embodiment of the disclosure provides a package device including a redistribution layer, an integrated passive device layer, a first port, and a second port. The integrated passive device layer contacts the redistribution layer. The integrated passive device layer has at least one capacitor. The at least one capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is provided opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance.

Abstract: Disclosed is an electroluminescent display device including a first pixel including a first sub pixel configured to emit first colored light, a second sub pixel configured to emit second colored light, and a third sub pixel configured to emit third colored light, a first electrode in the first sub pixel, an emission layer on the first electrode, a second electrode on the emission layer, and a first charge blocking layer provided below the second electrode and configured to prevent a light emission in the emission layer, wherein the first electrode is electrically connected with a driving thin film transistor in a first contact area provided in the first sub pixel, and the first charge blocking layer is overlapped with the first contact area.

Abstract: A method includes implanting a first dopant having a first dopant type into a substrate to define a plurality of source/drain (S/D) regions. The method further includes implanting a second dopant having the first dopant type into the substrate to define a channel region between adjacent S/D regions of the plurality of S/D regions, wherein a dopant concentration of the second dopant in the channel region is less than half of a dopant concentration of the first dopant in each of the plurality of S/D regions. The method further includes forming a gate stack over the channel region. The method further includes electrically coupling each of the plurality of S/D regions together.

Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Abstract: The present application relates to a fabrication method for a double-sided capacitor. The fabrication method for the double-sided capacitor includes the following steps: providing a substrate; forming a stack structure on the substrate; forming a capacitor hole in a direction perpendicular to the substrate to penetrate the stack structure, wherein the stack structure includes sacrificial layers and supporting layers alternately stacked; forming an auxiliary layer to cover the sidewall of the capacitor hole; forming a first electrode layer to cover the surface of the auxiliary layer; removing a part of the supporting layer on the top of the stack structure; removing the sacrificial layers and the auxiliary layer simultaneously along the opening; and forming a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer, wherein the gap is at least filled with the dielectric layer.

Abstract: The present disclosure discloses an evaporation method, an evaporation mask assembly, a display panel and a display device, which can reduce the complexity of the manufacturing process of the display panel and improve the yield of the display panel. The evaporation method may comprise: performing a first evaporation on a base substrate by using a first mask to form a first evaporation sub-pattern on the base substrate, wherein the first mask has a first opening area; and performing a second evaporation on the base substrate by using a second mask to form a second evaporation sub-pattern on the base substrate, wherein the second mask has a second opening area; wherein the combination of the first and second evaporation sub-patterns forms an evaporation pattern.

Abstract: An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.

Abstract: A system and method for fabricating on-die metal-insulator-metal capacitors capable of supporting relatively high voltage applications and increasing capacitance per area are described. In various implementations, an integrated circuit includes multiple metal-insulator-metal (MIM) capacitors. The MIM capacitors are formed between two signal nets such as two different power rails, two different control signals, or two different data signals. The integrated circuit includes multiple intermediate metal layers (or metal plates) formed between two signal nets. In high voltage regions, a MIM capacitor has one or more intermediate metal plates formed as floating plates between electrode metal plates. The floating plates have no connection to any power supply reference voltage level used by the integrated circuit.

Abstract: A capacitor structure and a method of preparing the same are provided. The method includes the followings. A substrate is provided. A stacked layer is formed on the substrate. A plurality of first via holes penetrating through the stacked layer are formed. The first via hole is filled with a conductive material to form a conductive pillar. A plurality of second via holes penetrating through the stacked layer are formed at a preset radius with the conductive pillar as an axis. The second via hole surrounds the conductive pillar circumferentially. The second via hole is filled with the conductive material to form an annular top electrode with a second gear.

Abstract: An organic light-emitting display device includes: a substrate; a pixel electrode on the substrate; an auxiliary electrode spaced apart from the pixel electrode; a first insulating film between the pixel electrode and the auxiliary electrode and covering an end of the pixel electrode and an end of the auxiliary electrode; an intermediate layer on the pixel electrode and including an emission layer; an opposite electrode covering the intermediate layer and contacting the auxiliary electrode; and a passivation layer covering the opposite electrode.

Abstract: The present application relates to semiconductor structure and forming method comprising: forming substrate, wherein plurality of capacitive contacts are provided in the substrate, plurality of electrically conductive contact pads are provided at surface of the substrate to be correspondingly connected to plurality of capacitive contacts on one-to-one basis, and a space is present between every two adjacent electrically conductive contact pads; forming filling layer that is fully filled in the space; forming stacked structure at the filling layer and surface of the electrically conductive contact pads, wherein the stacked structure includes plurality of supporting layers stacked one-on-another along direction perpendicular to the substrate, the filling layer is in contact with the supporting layer disposed at bottom of the stacked structure, and etching selection ratio between the filling layer and the supporting layer in contact therewith is greater than preset value; and etching the stacked structure to for

Abstract: Microwave packaging uses signal vias and interposers, such as metal lead frame interposers. For example, the microwave circuit die includes signal vias that electrically connect the top side and the bottom side of the die. Microwave signal circuitry on the die have signal paths that are electrically connected to the top side of the signal vias. The microwave signal circuitry typically may have an operating frequency of 300 MHz or faster. The bottom side of the signal vias are electrically connected to corresponding areas on the top side of the interposer. The bottom side of the die may also include a ground plane, with ground vias that electrically connect the top side of the die to the ground plane.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. A pixel region is provided with a light emission function layer on a base substrate of the display substrate, and a separation region is provided with at least one first barrier structure. The first barrier structure includes a stopper pattern and a first separation component. A side surface of the first separation component has a recess, and a portion of the light emission function layer extending to the separation region is disconnected on the side of the first separation component. The separation region is provided with an inorganic layer structure on the base substrate. The inorganic layer structure includes multiple stacked inorganic film layers, the stopper pattern is located between two adjacent inorganic film layers and the first separation component is located on a side of the inorganic layer structure away from the base substrate.

Abstract: A semiconductor device includes a target layer disposed on a substrate, and a crack sensor for detecting a crack generated in the target layer. The crack sensor includes a first conductive pattern positioned at a bottom surface of the target layer, a second conductive pattern positioned on a top surface of the target layer, the top surface being opposite to the bottom surface of the target layer, a plurality of resistors, and nodes. The plurality of resistors are connected in parallel to each other through the first conductive pattern and the second conductive pattern. Each of the plurality of resistors is disposed to substantially penetrate the target layer.

Abstract: A semiconductor structure includes an interfacial layer disposed over a semiconductor layer, a high-k gate dielectric layer disposed over the interfacial layer, where the high-k gate dielectric layer includes a first metal, a metal oxide layer disposed between the high-k gate dielectric layer and the interfacial layer, where the metal oxide layer is configured to form a dipole moment with the interfacial layer, and a metal gate stack disposed over the high-k gate dielectric layer. The metal oxide layer includes a second metal different from the first metal, and a concentration of the second metal decreases from a top surface of the high-k gate dielectric layer to the interface between the high-k gate dielectric layer and the interfacial layer.

Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.