Abstract: An array substrate and a manufacturing method thereof are provided. The array substrate includes a display pixel area for providing pixel units arranged in an array. The array substrate further includes: a base substrate, a first insulating layer, a second insulating layer, and a first conductive pattern layer. The first insulating layer is provided on the base substrate, grooves are provided in the first insulating layer, and the grooves are provided in the display pixel area. The second insulating layer is provided on the first insulating layer, and the second insulating layer is also filled into the grooves. The first conductive pattern layer is provided on the second insulating layer. By providing the grooves, the array substrate may have better impact resistance and bending resistance.

Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.

Abstract: A display device includes a substrate, first thin film transistors and second thin film transistors. A gate line is formed integrally with a first gate electrode of the first thin film transistors. An isolation insulating layer is disposed over a first gate insulating layer of the first thin film transistors. A second active layer of the second thin film transistors is disposed on the isolation insulating layer. An overlap pattern is disposed on the isolation insulating layer to be connected to the gate line. The overlap pattern includes a first overlap pattern disposed on the isolation insulating layer and formed of substantially the same material as the second active layer. A second overlap pattern is disposed on the first overlap pattern.

Abstract: A laminated device chip manufacturing method includes: a first wafer processing step of exposing a first resin layer disposed in first grooves to an undersurface side of a first wafer by thinning the first wafer fixed to a first support; a laminating step of laminating the undersurface side of the first wafer and a top surface side of a second wafer to each other such that the first resin layer exposed to the undersurface side of the first wafer and a second resin layer disposed in second grooves of the second wafer coincide with each other; a second wafer processing step of exposing the second resin layer disposed in the second grooves to an undersurface side of the second wafer by thinning the second wafer; and a resin layer cutting step of manufacturing laminated device chips by cutting the first resin layer and the second resin layer.

Abstract: A light emitting device may include a first electrode disposed on a substrate, and a second electrode spaced apart from the first electrode, the first electrode and the second electrode being disposed on a same layer; an insulating pattern disposed between the first electrode and the second electrode, and overlapping a portion of the first electrode and a portion of the second electrode; and at least one light emitting element disposed on the insulating pattern, and including a first end and a second end in a longitudinal direction of the at least one light emitting element; a first bank disposed on the first electrode, and a second bank disposed on the second electrode; a first reflective electrode disposed on the first bank and electrically connected with the first electrode; and a second reflective electrode disposed on the second bank and electrically connected with the second electrode.

Abstract: A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material.

Abstract: A conductive pattern forming method according to an embodiment includes: forming a first conductive pattern on a substrate; sequentially forming a release layer and a conductive layer on a transfer substrate that includes a mask; irradiating intense pulsed light (IPL) to the substrate where the first conductive pattern is formed; placing the transfer substrate on the substrate; transferring a portion of the conductive layer, corresponding to an opening of the mask, onto the substrate by irradiating the IPL to the transfer substrate to form a second conductive pattern on the substrate.

Abstract: A display device includes a first substrate, a first electrode on the first substrate, a second electrode on the first substrate and spaced from the first electrode, a plurality of light-emitting elements each having respective end portions on the first and second electrodes, a first transistor having a first end connected to the first electrode and a second end grounded, and a second transistor having a first end connected to the second electrode and a second end grounded, wherein the first transistor is forward-biased to the first electrode, and the second transistor is reverse-biased to the second electrode.

Abstract: A first frame includes portions of a first short side surface and a first long side surface, in which a plurality of conductor layers to which a plurality of DC electrode terminals are connected, and a plurality of insulating layers arranged between the plurality of conductor layers are stacked. Further, a second frame includes portions of a second short side surface and a second long side surface.

Abstract: A light emitting element includes a first semiconductor layer; an emission layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the emission layer; an electrode layer disposed on the second semiconductor layer; and an insulating film surrounding side surfaces of the first semiconductor layer, the emission layer, and the second semiconductor layer and surrounding a portion of the electrode layer at an end portion of the light emitting element on which the electrode layer is disposed. The electrode layer includes a first surface adjacent to the second semiconductor layer; a second surface facing the first surface and having a width less than a width of the first surface; and a side surface that connects the first surface and the second surface and has a slope in a range of about 75° to about 90° with respect to the first surface of the electrode layer.

Abstract: Display panel and display device are provided. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving transistor and an initialization transistor. The initialization transistor is configured to provide an initialization signal for a preset node. The preset node is a gate of the driving transistor, or an anode of the light-emitting element. The pixel circuit includes an oxide semiconductor transistor and a silicon transistor. An active layer of the oxide semiconductor transistor includes an oxide semiconductor, and an active layer of the silicon transistor includes silicon. The pixel circuit includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes a first initialization transistor. The second pixel circuit includes a second initialization transistor. An active layer of the first initialization transistor is connected to an active layer of the second initialization transistor through a first connection wire.

Abstract: There is provided a technique capable of forming a sufficiently flat film. According to one aspect of the technique, there is provided a substrate processing method including: forming a metal-containing multi-layer film structure on a substrate by alternately performing: (a) forming a metal-containing film on the substrate; and (b) supplying a process gas to the substrate so as to perform one or both of (b-1) forming a crystal layer separation film to a surface of the metal-containing film and (b-2) removing abnormal growth nuclei at the surface of the metal-containing film.

Abstract: A quantum-technological, micro-electro-optical or micro-electronic or photonic system includes a planar substrate of a direct or indirect semiconductor material. The system includes a microelectronic circuit including at least one transistor or diode. The system further includes a micro-optical subdevice and one or more nanoparticles, having one or more color centers. The surface of the of the planar substrate has a portion of a solidified colloidal film which is firmly bonded to the surface of the substrate. The portion of the solidified colloidal film includes the one or more nanoparticles. The system further includes a light-emitting electro-optical component. The light-emitting electro-optical component interacts optically with the micro-optical subdevice. The light-emitting electro-optical component interacts electrically and/or optically with the electrical component through the micro-optical subdevice.

Abstract: Various methods for manufacturing semiconductor structures are provided. An embodiment method includes forming a first patterned hard mask and epitaxial layer on a semiconductor substrate, and forming a first doped region in the epitaxial layer by performing a first implantation through the first patterned hard mask. A second doped region is formed in the epitaxial layer by performing a second implantation through the first patterned hard mask, with the first doped region at least partially overlapping the second doped region. A second patterned hard mask is formed, which surrounds the first patterned hard mask and covers at least a portion of the first doped region. A third doped region is formed in the epitaxial layer by performing a third implantation through the first patterned hard mask and the second patterned hard mask.

Abstract: Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.

Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Abstract: A display substrate and a display device. The display substrate includes: a plurality of pixel islands, a first opening, a second opening and a first passage region. Each pixel island includes at least one pixel, each pixel includes a plurality of first driving lines, the first passage region is provided with a plurality of first connection lines, each of the plurality of pixel islands further includes a plurality of transfer lines, and the plurality of transfer lines are arranged in different layers from the plurality of first driving lines and cross each other to form a plurality of overlapping regions; the plurality of transfer lines are electrically connected with the plurality of first driving lines through via holes located in part of the overlapping regions, and the transfer lines in two adjacent pixel islands are respectively connected with the plurality of first connection lines in the first passage region.

Abstract: Transistors using nitride semiconductor layers as channels were experimentally manufactured. The nitride semiconductor layers were all formed through a sputtering method. A deposition temperature was set at less than 600° C., and a polycrystalline or amorphous InxGayAlzN layer was obtained. When composition expressed with a general expression InxGayAlzN (where x+y+z=1.0) falls within a range of 0.3?x?1.0 and 0?z<0.4, a transistor 1a exhibiting an ON/OFF ratio of 102 or higher can be obtained. That is, even a polycrystalline or amorphous film exhibits electric characteristics equal to those of a single crystal. Therefore, it is possible to provide a semiconductor device in which constraints to manufacturing conditions are drastically eliminated, and which includes an InGaAlN-based nitride semiconductor layer which is inexpensive and has excellent electric characteristics as a channel.

Abstract: A display panel includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a display element located in the second region and including a pixel electrode, an opposite electrode, an intermediate layer; a multi-layered film arranged between the substrate and the pixel electrode and including an organic insulating layer and an inorganic layer on the organic insulating layer; and at least one groove formed in the multi-layered film and located in the third region, wherein at least one organic material layer is included in the intermediate layer and is disconnected by the at least one groove.

Abstract: Provided is a display substrate, which includes a base substrate, a circuit structure layer disposed on the base substrate, multiple ultrasonic sensing elements and multiple micro light-emitting elements. The multiple ultrasonic sensing elements are disposed on a side of the circuit structure layer away from the base substrate, and are electrically connected to the circuit structure layer, and the multiple light-emitting elements are disposed on the side of the circuit structure layer away from the base substrate, and are electrically connected to the circuit structure layer. An orthographic projection of the multiple ultrasonic sensing elements on the base substrate does not overlap with an orthographic projection of the multiple micro light-emitting elements on the base substrate.