Patents Examined by Ori Nadav
  • Patent number: 11570914
    Abstract: An electronic device including a flexible display panel is provided. The electronic device includes a display panel, a first component, a movable module, and a housing. The housing includes a first movable portion, a second component, and a third component. The third component includes a first space where the first component is stored. The display panel includes a flexible display portion. The display portion includes a first region, a second region, and a third region. The first region is fixed to the second component. The second region is fixed to the first component stored in the third component. The movable module has a function of holding a first angle that is formed between the second component and the third component by the first movable portion. The third region positioned between the first region and the second region has a function of forming a curved surface according to the first angle. The first component slides in the first space according to the first angle.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: January 31, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akio Endo, Shigeru Onoya, Takahiro Fukutome
  • Patent number: 11557663
    Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 11538908
    Abstract: A semiconductor device (100, 100?, 100?) and a method for manufacturing a semiconductor device (100, 100?, 100?). The semiconductor device (100, 100?, 100?) includes a substrate (104, 106), a GaN layer (112), and an AlGaN layer (114). The GaN layer (112) is located between the substrate (104, 106) and the AlGaN layer (114). The device further includes at least one contact (130, 132, 134), comprising a central portion (150) and an edge portion (152), and a passivation layer (160) located at least between the edge portion (152) of the contact (130, 132, 134) and the AlGaN layer (114). The edge portion (152) is spaced apart from an upper surface of the passivation layer (160). The edge portion (152) may be spaced apart from the passivation layer (160) by a further layer (170) or by an air gap (172).
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: December 27, 2022
    Assignee: Nexperia B.V.
    Inventors: Johannes Josephus Theodorus Marinus Donkers, Hans Broekman
  • Patent number: 11515335
    Abstract: The application discloses a method adapted to manufacture an array substrate and a display panel. The method includes: form a photoresist layer, a source and a drain; post-baking the photoresist layer, so that the photoresist layer flows to the position of a channel; etching a semiconductor layer to obtain a preset pattern; and peeling off the photoresist layer.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 29, 2022
    Assignee: HKC CORPORATION LIMITED
    Inventor: Bei Zhou Huang
  • Patent number: 11498832
    Abstract: A stacked semiconductor structure includes a first substrate. A multilayer interconnect is disposed over the first substrate. Metal sections are disposed over the multilayer interconnect. First bonding features are over the metal sections. A second substrate has a front surface. A cavity extends from the front surface into a depth D in the second substrate. A movable structure is disposed over the front surface of the second substrate and suspending over the cavity. The movable structure includes a dielectric membrane, metal units over the dielectric membrane and a cap dielectric layer over the metal units. Second bonding features are over the cap dielectric layer and bonded to the first bonding features. The second bonding features extend through the cap dielectric layer and electrically coupled to the metal units.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hua Chu, Chun-Wen Cheng
  • Patent number: 11503726
    Abstract: Disclosed is a display apparatus including an LED module having a first fastening member, a front bracket having a second fastening member on which the LED module is mounted by an attractive force generated between the first and second fastening members, and at least one level adjusting member disposed on the LED module and configured to adjust a level difference between the LED module and another adjacent LED module.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Huu Lam Vuong Nguyen, Bong Ju Lee, Kwang Sung Hwang
  • Patent number: 11488889
    Abstract: Cubic BAs is used in semiconductors to improve the thermal characteristics of a device. The BAs is used in device layers to improve thermal conductivity. The BAs also provides thermal expansion characteristics that are compatible with other semiconductors and thereby further improves reliability. The substrates of the semiconductors may also include vias that contain BAs. The BAs in the vias may contact the BAs in the device layers. Some vias may have a surface area to volume ratio of greater than 10 to better assist with device heat dissipation.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: November 1, 2022
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: John A. Starkovich, Jesse B. Tice, Vincent Gambin
  • Patent number: 11489038
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes conductive materials located in different levels of the apparatus, dielectric materials located in different levels of the apparatus, a first conductive contact, and a second conductive contact. One of the conductive materials is between two of the dielectric materials. One of the dielectric materials is between two of the conductive materials. The first conductive contact has a length extending through the conductive materials and the dielectric materials in a direction perpendicular to the levels of the apparatus. The first conductive contact is electrically separated from the conductive materials. The second conductive contact contacts a group of conductive materials of the conductive materials.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Qiang Tang
  • Patent number: 11482565
    Abstract: A solid-state imaging device and method of making a solid-state imaging device are described herein. By way of example, the solid-state imaging device includes a first wiring layer formed on a sensor substrate and a second wiring layer formed on a circuit substrate. The sensor substrate is coupled to the circuit substrate, the first wiring layer and the second wiring layer being positioned between the sensor substrate and the circuit substrate. A first electrode is formed on a surface of the first wiring layer, and a second electrode is formed on a surface of the second wiring layer. The first electrode is in electrical contact with the second electrode.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: October 25, 2022
    Assignee: Sony Group Corporation
    Inventors: Takeshi Yanagita, Keiji Mabuchi
  • Patent number: 11476317
    Abstract: A display device includes a plurality of pixels that is arrayed in a first direction and a second direction. Each pixel includes; a first sub-pixel, a second sub-pixel that is disposed to be adjacent to the first sub-pixel in the first direction, a third sub-pixel that is disposed to be adjacent to at least one of the first sub-pixel and the second sub-pixel in the second direction, and a light shielding portion that is disposed corresponding to the position on which the third sub-pixel is disposed, so as to limit a viewing angle of the third sub-pixel in the first direction.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 18, 2022
    Assignee: Sony Group Corporation
    Inventors: Yosuke Motoyama, Reo Asaki, Shingo Makimura
  • Patent number: 11476282
    Abstract: An active matrix substrate includes gate bus lines; source bus lines; a lower insulating layer; an oxide semiconductor TFT; and a pixel electrode, in which the oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode, a source electrode, and a first ohmic conductive portion that is coupled to the oxide semiconductor layer and the source electrode, the lower insulating layer includes a source opening portion exposing at least a portion of the source electrode, the first ohmic conductive portion is disposed on the lower insulating layer and in the source opening portion and is in direct contact with at least the portion of the source electrode in the source opening portion, and the first region of the oxide semiconductor layer is in direct contact with an upper surface of the first ohmic conductive portion.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 18, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Masaki Maeda, Tatsuya Kawasaki, Hideki Kitagawa, Yoshiharu Hirata
  • Patent number: 11469109
    Abstract: A semiconductor structure having metal contact features and a method for forming the same are provided. The method includes forming a dielectric layer covering an epitaxial structure over a semiconductor substrate and forming an opening in the dielectric layer to expose the epitaxial structure. The method includes forming a metal-containing layer over the dielectric layer and the epitaxial structure. The method includes heating the epitaxial structure and the metal-containing layer to transform a first portion of the metal-containing layer contacting the epitaxial structure into a metal-semiconductor compound layer. The method includes oxidizing the metal-containing layer to transform a second portion of the metal-containing layer over the metal-semiconductor compound layer into a metal oxide layer. The method includes applying a metal chloride-containing etching gas on the metal oxide layer to remove the metal oxide layer and forming a metal contact feature over the metal-semiconductor compound layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 11462538
    Abstract: A novel semiconductor device is provided. A back gate voltage of a transistor including a gate and a back gate is adjusted based on the operating temperature. The operating temperature is acquired by a temperature detector circuit. The temperature detection circuit outputs the temperature information as a digital signal. The digital signal is input to a voltage control circuit. The voltage control circuit outputs a first voltage corresponding to the digital signal. The back gate voltage is determined by a voltage in which a first voltage is added to a reference voltage.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 4, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Onuki, Takanori Matsuzaki, Tomoaki Atsumi, Takahiko Ishizu
  • Patent number: 11456437
    Abstract: An electroluminescence display device having a through-hole in a display area is discussed. The electroluminescence display device can include a substrate, a through-hole, an inner dam, and a hole-trench. The substrate includes a display area where a plurality of pixels for displaying images are arranged, and a non-display area surrounding the display area. The through-hole is arranged inside the display area. The inner dam surrounds the through-hole. The hole-trench surrounds the inner dam, and is formed as the substrate is partially recessed as much as a certain thickness.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: September 27, 2022
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Junggi Kim
  • Patent number: 11450798
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a gate disposed on a quantum well stack; an insulating material disposed on the gate; and a conductive via extending through the insulating material and in conductive contact with the gate.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke
  • Patent number: 11422423
    Abstract: A structure for preventing deteriorations of a light-emitting device and retaining sufficient capacitor elements (condenser) required by each pixel is provided. A first passivation film, a second metal layer, a flattening film, a barrier film, and a third metal layer are stacked in this order over a transistor. A side face of a first opening provided with the flattening film is covered by the barrier film, a second opening is formed inside the first opening, and a third metal layer is connected to a semiconductor via the first opening and the second opening. A capacitor element that is formed of a lamination of a semiconductor of a transistor, a gate insulating film, a gate electrode, the first passivation film, and the second metal layer is provided.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 23, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Toru Takayama, Satoshi Murakami, Hajime Kimura
  • Patent number: 11404362
    Abstract: A wiring substrate includes a wiring layer and an insulation layer covering the wiring layer. The insulation layer includes an opening partially exposing the wiring layer. A seed layer continuously covers a wall surface of the opening and an upper surface of the insulation layer. The wiring substrate also includes a metal layer, a metal post, and an outer coating plating layer. The opening is filled with the seed layer and the metal layer formed on the seed layer. The metal post is formed on the metal layer and on the seed layer that is located on the insulation layer. The outer coating plating layer includes an upper portion, entirely covering an upper surface of the metal post, and a side portion, entirely covering a side surface of the metal post and exposing an outer end surface of the seed layer. The side portion is thinner than the upper portion.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: August 2, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Takashi Arai
  • Patent number: 11404423
    Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary integrated circuit (IC) device includes a FinFET disposed over a doped region of a first type dopant. The FinFET includes a first fin having a first width doped with the first type dopant and first source/drain features of a second type dopant. The IC device further includes a fin-based well strap disposed over the doped region of the first type dopant. The fin-based well strap connects the doped region to a voltage. The fin-based well strap includes a second fin having a second width doped with the first type dopant and second source/drain features of the first type dopant. The second width is greater than the first width. For example, a ratio of the second width to the first width is greater than about 1.1 and less than about 1.5.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventor: Jhon Jhy Liaw
  • Patent number: 11393899
    Abstract: High voltage semiconductor device and manufacturing method thereof are disclosed. The high voltage semiconductor device includes a semiconductor substrate, a gate structure, at least one first isolation structure and at least one second isolation structure, and at least one first drift region. The gate structure is disposed on the semiconductor substrate. The first isolation structure and the second isolation structure are disposed in an active area of the semiconductor substrate at a side of the gate structure. An end of the second isolation structure is disposed between the first isolation structure and the gate structure, and an end of the first isolation structure is disposed between the first doped region and the second isolation structure. A bottom of the at least one first isolation structure and a bottom of the at least one second isolation structure are deeper than a bottom of the first drift region.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: July 19, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Chao Sun
  • Patent number: 11374039
    Abstract: This disclosure provides an array substrate and a method of manufacturing the same. The method includes: forming a switch element; etching on an extension of a gate insulation layer to obtain a second amorphous silicon layer, a second N-type amorphous silicon layer and a light sensing metal at the same time to form a photosensor; forming a light sensing layer and a passivation layer on a source metal, a drain metal, and the light sensing metal; and forming a first light sensing layer and a first passivation layer on the source metal and the drain metal, and forming a second light sensing layer and a second passivation layer on the light sensing metal by using a second mask.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: June 28, 2022
    Assignees: HKC CORPORATION LIMITED, CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: En-Tsung Cho, Feng Yun Yang