Patents Examined by Ori Nadav
  • Patent number: 11201286
    Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: December 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Matthew N. Rocklein, D. V. Nirmal Ramaswamy
  • Patent number: 11201129
    Abstract: Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Sridhar Balakrishnan, Mark Bohr
  • Patent number: 11177141
    Abstract: A method for packaging a chip and a chip package structure are provided. The method is used to package the chip including an acoustic filter. The packaging substrate and the device wafer are welded together, wherein the edge of the device wafer is chamfered, the packaging substrate is provided with a groove, the chamfered portion of device wafer is aligned with the groove on the substrate, and then a mask is disposed. The surface of the mask facing the device wafer is an inclined surface, forming a wedge-shaped opening. A package resin material is printed, wherein the package resin material falls into the groove through the inclined surface of the mask, and a package resin film is formed between the groove and the chamfer. The mask is removed along the first surface toward the second surface. The package resin is cured in a position where the resin film is located.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 16, 2021
    Assignee: JWL (Zhejiang) Semiconductor Co., Ltd
    Inventor: Linping Li
  • Patent number: 11145679
    Abstract: A method for manufacturing an active matrix board includes (E) a step of forming a source contact hole and a drain contact hole in an interlayer insulating layer such that a portion of a source contact region of an oxide semiconductor layer and a portion of a drain contact region thereof are exposed and forming a connecting portion contact hole in the interlayer insulating layer and a lower insulating layer such that a portion of a lower conductive layer is exposed; and (F) a step of forming a source electrode, a drain electrode, and an upper conductive layer on the interlayer insulating layer; and the step (E) includes (e-1) a step of forming a photoresist film on the interlayer insulating layer and (e-2) a step of forming a photoresist layer in such a manner that the photoresist film is exposed to light using a multi-tone mask and is then developed.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: October 12, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kengo Hara, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Masahiko Suzuki, Setsuji Nishimiya, Masamitsu Yamanaka, Teruyuki Ueda, Hitoshi Takahata
  • Patent number: 11145758
    Abstract: A structure capable of effectively preventing dopant diffusion from source/drain regions into an underlying semiconductor-on-insulator (SOI) layer of fully-depleted SOI transistors with U-shaped channels is provided. By inserting a dopant diffusion barrier layer between an SOI layer of an SOI substrate and a doped extension layer from which source/drain extension regions are derived, the undesired dopant diffusion from the source/drain extension regions into the underlying SOI layer can be prevented.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Robert H. Dennard, Bruce B. Doris, Terence B. Hook
  • Patent number: 11127844
    Abstract: A semiconductor device includes: a drift layer; a mesa region that is interposed between adjacent trenches on the drift layer; a gate electrode buried in each trench through a gate insulating film; a base region of buried in the mesa region; a plurality of emitter regions that are periodically buried in a surface layer portion of the base region along a longer direction of the trench; and contact regions that are alternately buried in the longer direction together with the emitter regions such that each emitter region is interposed between the contact regions, are deeper than the emitter region, and extend immediately below the emitter region so as to be separated from each other, a contact-region contact-width in the longer direction defined in a surface of the contact region being less than an emitter-region contact-width in the longer direction defined in a surface of the emitter region.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: September 21, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hitoshi Abe, Hiroshi Miyata, Hidenori Takahashi, Seiji Noguchi, Naoya Shimada
  • Patent number: 11101278
    Abstract: A semiconductor memory device includes: a substrate including a cell region and a connection region; a first word line stack comprising a plurality of first word lines that extend to the connection region and are stacked on the cell region; a second word line stack comprising a plurality of second word lines that extend to the connection region and are stacked on the cell region, the second word line being adjacent to the first word line stack; vertical channels in the cell region of the substrate, the vertical channels being connected to the substrate and coupled with the plurality of first and second word lines; a bridge region that connects the first word lines of the first word line stack with the second word lines of the second word line stack; and a local planarized region under the bridge region.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: August 24, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-kook Park, Hong-soo Kim, Tae-keun Cho
  • Patent number: 11075209
    Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: July 27, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Yuichi Nakao
  • Patent number: 11074296
    Abstract: To derive a query which can be joined and which gives non-zero pieces of data even if joined. A query generation assist method to assist generation of a query to extract data from a database includes: a first step of accepting, at the computer, a condition of extracting data to be acquired from the database as a data extraction condition; a second step of extracting, as graph data and at the computer, data which can be joined in data of the database; a third step of extracting subgraphs at the computer based on the data extraction condition from the graph data, and acquiring the subgraphs as query candidates; and a fourth step of calculating, at the computer, rank values of the query candidates and outputting the query candidates ranked according to the rank values.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 27, 2021
    Assignee: HITACHI, LTD.
    Inventors: Yohsuke Ishii, Yuuya Isoda
  • Patent number: 11069678
    Abstract: A logic gate cell structure is disclosed. The logic gate cell structure includes a substrate, a channel layer disposed over the substrate, and a field-effect transistor (FET) contact layer disposed over the channel layer. The FET contact layer is divided by an isolation region into a single contact region and a combined contact region. The channel layer and the FET contact layer form part of a FET device. A collector layer is disposed within the combined contact region over the FET contact layer to provide a current path between the channel layer and the collector layer though the FET contact layer. The collector layer, a base layer, and an emitter layer form part of a bipolar junction transistor.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 20, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Peter J. Zampardi, Brian G. Moser, Denny Limanto
  • Patent number: 11049886
    Abstract: A thin film transistor array substrate includes: a substrate on which a thin film transistor and a storage capacitor are formed. The storage capacitor includes a first electrode plate formed on the substrate, a gate isolation layer or an etching stopper layer formed on the first electrode plate, and a second electrode plate formed on the gate isolation layer or the etching stopper layer. The etching stopper layer may be formed on the gate isolation layer, of which one is partially etched and removed such that there is only one of the gate isolation layer and the etching stopper layer existing between the two electrode plates of the storage capacitor so as to reduce the overall thickness of the isolation layer of the storage capacitor. Thus, the capacitor occupies a smaller area and a higher aperture ratio may be achieved.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 29, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaowen Lv
  • Patent number: 11018216
    Abstract: In accordance with an embodiment, an electrical element includes a first portion of a first dielectric material between a first portion of a first electrical conductor and a first portion of a second electrical conductor and a second portion of the first dielectric material between a second portion of the first electrical conductor and a first portion of a third electrical conductor. In accordance with another embodiment, an electrical component has a plurality of dopant regions formed in a semiconductor material, where the dopant regions include a plurality of dopant regions formed in a dopant region of the same conductivity type. A plurality of dopant regions of an opposite conductivity type are formed in corresponding dopant regions of the first conductivity type. A metallization system is formed over the semiconductor material, where a portion of the metallization system contacts the semiconductor material.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: May 25, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Richard Scott Burton, Karel Ptacek
  • Patent number: 10913653
    Abstract: A method for fabricating a MEMS sensor device. The method can include providing a substrate, forming an IC layer overlying the substrate, forming an oxide layer overlying the IC layer, forming a metal layer coupled to the IC layer through the oxide layer, forming a MEMS layer having a pair of designated sense electrode portions and a designated proof mass portion overlying the oxide layer, forming a via structure within each of the designated sense electrode portions, and etching the MEMS layer to form a pair of sense electrodes and a proof mass from the designated sense electrode portions and proof mass portions, respectively. The via structure can include a ground post and the proof mass can include a sense comb. The MEMS sensor device formed using this method can result is more well-defined edges of the proof mass structure.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 9, 2021
    Assignee: MCUBE INC.
    Inventors: Ben (Wen-Pin) Chuang, M H (Ming-Hong) Kuo, W J (Wen-Chih) Chen, Tse-Hsi “Terrence” Lee
  • Patent number: 10886276
    Abstract: Provided are a semiconductor memory device including a capacitor and a method of fabricating the same. The capacitor may include a plurality of contacts that are electrically connected to the switching device, exposed on the top surface of a substrate, and are arranged in a first direction and a second direction different from the first direction, and the first direction and the second direction are parallel to the substrate; mold insulators that are formed on the substrate between the contacts adjacent to one another in the first direction from among the plurality of contacts, are formed to have a predetermined thickness and have a predetermined width in the second direction, and extend in a direction vertical to the substrate; bottom electrodes that have a vertical plate-like structure, are provided on and supported by sidewalls of the mold insulators, and are electrically and respectively connected to the plurality of contacts.
    Type: Grant
    Filed: September 18, 2016
    Date of Patent: January 5, 2021
    Assignee: Seoul National University R&DB foundation
    Inventor: Cheol Seong Hwang
  • Patent number: 10879250
    Abstract: A method for forming a semiconductor structure includes providing a substrate including a plurality of first isolation structures formed therein, wherein the first isolation structures are protruded from a surface of the substrate; conformally forming a semiconductor layer over the substrate and the first isolation structures; forming a sacrificial layer over the semiconductor layer to form a planar surface over the substrate; and removing the sacrificial layer, a portion of the semiconductor layer and a portion of each first isolation structure to form at least one first gate structure using a same etchant.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hung-Ling Shih, Yong-Shiuan Tsair, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Chieh-Fei Chiu
  • Patent number: 10811341
    Abstract: In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: October 20, 2020
    Assignee: Amkor Technology Singapore Holding Pte Ltd.
    Inventors: Dong Joo Park, Jin Seong Kim, Ki Wook Lee, Dae Byoung Kang, Ho Choi, Kwang Ho Kim, Jae Dong Kim, Yeon Soo Jung, Sung Hwan Cho
  • Patent number: 10811566
    Abstract: A light emitting module according to an embodiment comprises: a first support member having a first opening part and a second opening part; a second support member disposed in the first opening part in the first support member; a third support member disposed in the second opening part in the first support member; a first lead electrode disposed above the second support member; a second lead electrode disposed on the first support member and/or above the second support member; a light emitting chip disposed above the second support member and electrically connected to the first and second lead electrodes; a control component disposed above the third support member; and a conductive layer disposed underneath the first, second and third support members, wherein the first support member comprises a resin material, the second support material comprises a ceramic material and the third support member comprises a metal material.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 20, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Tomohiro Sampei
  • Patent number: 10685985
    Abstract: A pixel portion and a driver circuit driving the pixel portion are formed over the same substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor layer is used and a channel protective layer is provided over the oxide semiconductor layer serving as a channel formation region which is overlapped with the gate electrode. The driver circuit as well as the pixel portion is provided over the same substrate to reduce manufacturing costs.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Atsushi Umezaki
  • Patent number: 10644096
    Abstract: The frame wiring line provided in a frame region includes, at a bending section, a plurality of branch wiring lines being divided into a plurality of branches, wherein the plurality of branch wiring lines are arranged at at least two types of heights relative to a resin substrate.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: May 5, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masaki Yamanaka, Yohsuke Kanzaki, Takao Saitoh, Masahiko Miwa, Seiji Kaneko
  • Patent number: 10629734
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh