Abstract: A layout method includes: generating a design data including an electronic circuit; and generating a design layout by placing a cell corresponding to the electronic circuit. The cell includes a first transistor and a second transistor over the first transistor. The first transistor includes a gate extending in a first direction, a first active region arranged in a first layer and extending in a second direction, and a first conductive line and a second conductive line arranged on two sides of the first active region. The second transistor includes the gate, a second active region arranged in a second layer over the first layer and extending in the second direction, and a third conductive line and a fourth conductive line arranged on two sides of the second active region. At least one of the four conductive lines includes a first portion non-overlapped with the gate in the first direction.

Abstract: A process for mounting a light component on a carrier. The light component includes a generally planar substrate, on a first face of which submillimetre-sized electroluminescent semiconductor elements are epitaxied in the form of a matrix. The process is noteworthy in that it eliminates the need for a layer of filler material between the component and the carrier, while providing good thermal and electrical conductivity between the component and the carrier and high mechanical strength.

Abstract: Provided is a manufacturing method of an electronic device, including forming a circuit layer on a base layer, disposing a light emitting element for attachment over the circuit layer, disposing an insulating layer between the light emitting element and the circuit layer, and drying the insulation layer to attach the light emitting element with the insulating layer and the circuit layer.

Abstract: FinFET structures and methods of forming the same are disclosed. In a method, a fin is formed on a substrate, an isolation region is formed on opposing sides of the fin. The isolation region is doped with carbon to form a doped region, and a portion of the isolation region is removed to expose a top portion of the fin, wherein the removed portion of the isolation region includes at least a portion of the doped region.

Abstract: A heat radiation member excellent in electrical insulation and better in thermal conduction is provided. The heat radiation member includes a substrate composed of a composite material containing diamond and a metallic phase, an insulating plate provided on at least a part of front and rear surfaces of the substrate and composed of an aluminum nitride, and a single bonding layer interposed between the substrate and the insulating plate, the heat radiation member having thermal conductivity not lower than 400 W/m·K.

Abstract: A wafer lens array includes a wafer lens formed by arranging a plurality of plate members on a plane, each plate member including a first window configured to allow light for forming an optical image to pass through, a first light-shielding portion formed on an outer circumference of the first window and a second window formed on an outer circumferential side of the first light-shielding portion and configured to allow illumination light to pass through, and the wafer lens in plurality are coaxially layered and the layered wafer lenses are bonded and fixed together in a region of the second window.

Abstract: A display panel includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a display element located in the second region and including a pixel electrode, an opposite electrode, an intermediate layer; a multi-layered film arranged between the substrate and the pixel electrode and including an organic insulating layer and an inorganic layer on the organic insulating layer; and at least one groove formed in the multi-layered film and located in the third region, wherein at least one organic material layer is included in the intermediate layer and is disconnected by the at least one groove.

Abstract: Provided are a thermal conductive silicone composition having a favorable heat dissipation property; and a semiconductor device using such composition. The thermal conductive silicone composition contains: (A) an organopolysiloxane that has a kinetic viscosity of 10 to 100,000 mm2/s at 25° C., and is represented by the following average composition formula (1) R1aSiO(4-a)/2??(1) wherein R1 represents a hydrogen atom, a saturated or unsaturated monovalent hydrocarbon group having 1 to 18 carbon atoms or a hydroxy group, and a represents a number satisfying 1.8?a?2.2; (B) a silver powder having a tap density of not lower than 3.0 g/cm3, a specific surface area of not larger than 2.0 m2/g and an aspect ratio of 1 to 30; (C) an elemental gallium and/or gallium alloy having a melting point of 0 to 70° C. and being present at a mass ratio [Component (C)/{Component (B)+Component (C)}] of 0.001 to 0.1; and (D) a catalyst.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: A semiconductor device with stable electrical characteristics is provided. Alternatively, a semiconductor device having normally-off electrical characteristics is provided. A semiconductor device includes a gate electrode, a gate insulator, and an oxide semiconductor, the oxide semiconductor contains fluorine in a channel formation region, and a fluorine concentration in the channel formation region is higher than or equal to 1×1020 atoms/cm3 and lower than or equal to 1×1022 atoms/cm3. Note that fluorine is added by an ion implantation method.

Abstract: A semiconductor device including a capacitor whose charge capacity is increased while improving the aperture ratio is provided. Further, a semiconductor device which consumes less power is provided. A transistor which includes a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, an insulating film which is provided over the light-transmitting semiconductor film, and a first light-transmitting conductive film which is provided over the insulating film are included. The capacitor includes the first light-transmitting conductive film which serves as one electrode, the insulating film which functions as a dielectric, and a second light-transmitting conductive film which faces the first light-transmitting conductive film with the insulating film positioned therebetween and functions as the other electrode.

Abstract: Methods of fabrication and nano-sensor and nano-sensor array thereof are provided. A sensing electrode assembly can be patterned on a sacrificial layer of a substrate. The sensing electrode assembly can comprise a pair of contact pads and an electrode element coupled to and disposed between the pair of contact pads. The sensing electrode assembly can be formed on the patterned sensing electrode assembly. The sacrificial layer below a portion of the electrode element can be removed to obtain a suspended electrode element. The suspended electrode element can be oxidized at a first predetermined temperature to obtain a pair of electromigrated regions and a notch portion between the pair of the electromigrated regions. The notch portion can be used to detect a gaseous component in an ambient gas at a second predetermined temperature.

Abstract: A display panel and a display device are provided. By manufacturing a first via hole and a second via hole first, and then manufacturing a third via hole and a fourth via hole, the first via hole and the second via hole have been covered by a corresponding first drain electrode and first source electrode before performing hydrofluoric acid cleaning processes, and a first drain region and a first source region of a first oxide transistor are not affected by the hydrofluoric acid cleaning process, thereby allowing an oxide channel of the first oxide transistor to also be prevented from being affected.

Abstract: A solid-state imaging device and method of making a solid-state imaging device are described herein. By way of example, the solid-state imaging device includes a first wiring layer formed on a sensor substrate and a second wiring layer formed on a circuit substrate. The sensor substrate is coupled to the circuit substrate, the first wiring layer and the second wiring layer being positioned between the sensor substrate and the circuit substrate. A first electrode is formed on a surface of the first wiring layer, and a second electrode is formed on a surface of the second wiring layer. The first electrode is in electrical contact with the second electrode.

Abstract: A foldable display device is capable of improving a strength of a folding area and substantially reducing or minimizing a dead space of a non-folding area. The foldable display device includes: a display panel including a folding area and a non-folding area, and having a front surface and a back surface that are opposite each other; a window adjacent the front surface of the display panel; an auxiliary layer adjacent the back surface of the display panel; a first adhesive layer between the display panel and the window; and a second adhesive layer between the display panel and the auxiliary layer. A width of the window at the folding area is greater than a width of the window at the non-folding area.

Abstract: A display device includes a plurality of pixels that is arrayed in a first direction and a second direction. Each pixel includes; a first sub-pixel, a second sub-pixel that is disposed to be adjacent to the first sub-pixel in the first direction, a third sub-pixel that is disposed to be adjacent to at least one of the first sub-pixel and the second sub-pixel in the second direction, and a light shielding portion that is disposed corresponding to the position on which the third sub-pixel is disposed, so as to limit a viewing angle of the third sub-pixel in the first direction.

Abstract: A transparent display device is disclosed, which may improve yield and reduce a tact time, and may reduce resistance of a power line. The transparent display device includes a substrate provided with a display area, in which a plurality of subpixels are disposed, and a non-display area adjacent to the display area. The device further includes first and second pads provided over the substrate, a first pixel power line extended between a pad area in which the first pad and the second pad are disposed and the display area in a first direction, a first common power line extended between the first pixel power line and the display area in the first direction, a first common power connection electrode electrically connecting the second pad with the first common power line, and a second common power connection electrode disposed in a layer different from the first common power connection electrode, electrically connecting the second pad with the first common power line.

Abstract: The present application discloses a pixel structure and a display device. The pixel structure includes a scan line having a branch structure; and a semiconductor pattern intersecting with the scan line and the branch structure. The semiconductor pattern includes: a first channel region disposed below the scan line; a second channel region disposed below the branch structure; and doping regions respectively disposed at two sides of the first channel region and at two sides of the second channel region. Wherein, the width of the second channel region is less than the width of the first channel region. The pixel structure may improve the display performance of the display screen.

Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.

Abstract: Embodiments of methods to form three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions.