Patents Examined by Ori Nadav
  • Patent number: 10497560
    Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Tsu-Hui Su, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 10453953
    Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 22, 2019
    Assignee: VISHAY-SILICONIX
    Inventors: Kyle Terrill, Yuming Bai, Deva Pattanayak, Zhiyun Luo
  • Patent number: 10446647
    Abstract: A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10446608
    Abstract: A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 15, 2019
    Assignee: NXP USA, INC.
    Inventor: Anirban Roy
  • Patent number: 10431675
    Abstract: A carbon nanotube triode apparatus includes a plurality of Horizontally Aligned Single Wall Carbon Nano Tubes (HA-SWCNT) disposed on an electrically insulating thermally conductive substrate. A first contact is disposed on the substrate and electrically coupled to a first end of the HA-SWCNT. A second contact is disposed on the substrate and separated from a second end of the HA-SWCNT by a gap. A gate terminal is coincident with a plane of the substrate.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: October 1, 2019
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Ahmad Ehteshamul Islam, Benji Maruyama
  • Patent number: 10418439
    Abstract: At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: September 17, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig-Guitart, Peter Moens, Zia Hossain
  • Patent number: 10411086
    Abstract: In accordance with an embodiment, a method of manufacturing an electrical component that may include a high voltage capacitor that includes providing a semiconductor material of a second conductivity type in which first doped region of a first conductivity type is formed. A plurality of doped regions of the first conductivity type and a plurality of doped regions of the second conductivity type are formed in the first doped region. A first p-n junction is formed between first doped regions of the first and second conductivity types and a second p-n junction is formed between second doped regions of the first and second conductivity types. A metallization system is formed above the doped regions so that capacitors are formed by a parallel connection of a first metal layer to a polysilicon layer and the first metal layer to a second metal layer.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: September 10, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Richard Scott Burton, Karel Ptacek
  • Patent number: 10411137
    Abstract: Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: September 10, 2019
    Assignee: ABLIC Inc.
    Inventor: Tomomitsu Risaki
  • Patent number: 10403716
    Abstract: A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 3, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10403498
    Abstract: The present invention pertains to a group III-V compound semiconductor nanowire able to be used in a group III-V compound semiconductor MOSFET (FET) operational at a small subthreshold (100 mV/dec or less). A side face of the group III-V compound semiconductor nanowire is a (?110) plane constituted of a very small (111) plane. The group III-V compound semiconductor nanowire has, e.g., a first layer having a (111)A plane as a side face thereof, and a second layer having a (111)B plane as a side face thereof. The first layer and the second layer are stacked alternatingly in the axial direction.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: September 3, 2019
    Assignees: NATIONAL UNIVERSITY CORPORATION HAKKAIDO UNIVERSITY, JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Takashi Fukui, Katsuhiro Tomioka
  • Patent number: 10396000
    Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 27, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Tenko Yamashita, Chun-Chen Yeh, Hui Zang
  • Patent number: 10388563
    Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rak Hwan Kim, Byung Hee Kim, Sang Bom Kang, Jong Jin Lee, Eun Ji Jung
  • Patent number: 10381585
    Abstract: A thin film transistor includes a gate electrode, a insulating medium layer and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating medium layer. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating medium layer. The semiconducting structure includes a carbon nanotube structure. The second electrode is located on the second end.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 13, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Yuan-Hao Jin, Tian-Fu Zhang, Qun-Qing Li
  • Patent number: 10373989
    Abstract: A thin-film transistor (TFT) array substrate includes a TFT arrangement and a storage capacitor. A gate insulation layer has a portion interposed between two electrode plates of the storage capacitor and thinner than a remaining portion of the gate insulation layer and thus, the thickness of insulation between the electrode plates of the storage capacitor is reduced so that the area of the opposite surfaces of the capacitor can be made smaller and an increased aperture ratio can be achieved.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: August 6, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaowen Lv, Chihyu Su
  • Patent number: 10374180
    Abstract: A thin film transistor includes a gate, an insulating medium layer and a Schottky diode. The Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode is located on the surface of the insulating medium layer and includes a first metal layer and a second metal layer. The second electrode is located on the surface of the insulating medium layer and includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure includes a carbon nanotube structure.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 6, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Xiao-Yang Xiao, Ying-Cheng Wang, Yuan-Hao Jin, Tian-Fu Zhang, Qun-Qing Li
  • Patent number: 10366896
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to form a second spacer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: July 30, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Fan Chang, Yen-Liang Wu, Wen-Tsung Chang, Jui-Ming Yang, Jie-Ning Yang, Chi-Ju Lee, Chun-Ting Chiang, Bo-Yu Su, Chih-Wei Lin, Dien-Yang Lu
  • Patent number: 10361233
    Abstract: A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 10333064
    Abstract: This disclosure provides embodiments for the formation of vertical memory cell structures that may be implemented in RRAM devices. In one embodiment, memory cell area may be increased by varying word line height and/or word line interface surface characteristics to ensure the creation of a grain boundary that is suitable for formation of conductive pathways through an active layer of an RRAM memory cell. This may maintain continuum behavior while reducing random cell-to-cell variability that is often encountered at nanoscopic scales. In another embodiment, such vertical memory cell structures may be formed in multiple-tiers to define a three-dimensional RRAM memory array. Further embodiments also provide a spacer pitch-doubled RRAM memory array that integrates vertical memory cell structures.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Gurtej Sandhu
  • Patent number: 10325939
    Abstract: A method is provided for manufacturing a thin film transistor array substrate, which includes: a substrate on which a thin film transistor and a storage capacitor are formed on the substrate. The storage capacitor includes a first electrode plate formed on the substrate, a gate isolation layer or an etching stopper layer formed on the first electrode plate, and a second electrode plate formed on the gate isolation layer or the etching stopper layer. The etching stopper layer may be formed on the gate isolation layer, of which one is partially etched and removed such that there is only one of the gate isolation layer and the etching stopper layer existing between the two electrode plates of the storage capacitor so as to reduce the overall thickness of the isolation layer of the storage capacitor. Thus, the capacitor occupies a smaller area and a higher aperture ratio may be achieved.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: June 18, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaowen Lv
  • Patent number: 10326007
    Abstract: Methods of forming a graded SiGe percentage PFET channel in a FinFET or FDSOI device by post gate thermal condensation and oxidation of a high Ge percentage channel layer and the resulting devices are provided. Embodiments include forming a gate dielectric layer over a plurality of Si fins; forming a gate over each fin; forming a HM and spacer layer over and on sidewalls of each gate; forming a cavity in each fin adjacent to the gate and spacer layer; epitaxially growing an un-doped high percentage SiGe layer in each cavity and along sidewalls of each fin; thermally condensing the high percentage SiGe layer, an un-doped low percentage SiGe formed underneath in the substrate and fins; and forming a S/D region over the high percentage SiGe layer in each u-shaped cavity, an upper surface of the S/D regions below the gate dielectric layer.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George Robert Mulfinger, Ryan Sporer, Timothy J. McArdle, Judson Robert Holt