Patents Examined by Ori Nadav
  • Patent number: 10811566
    Abstract: A light emitting module according to an embodiment comprises: a first support member having a first opening part and a second opening part; a second support member disposed in the first opening part in the first support member; a third support member disposed in the second opening part in the first support member; a first lead electrode disposed above the second support member; a second lead electrode disposed on the first support member and/or above the second support member; a light emitting chip disposed above the second support member and electrically connected to the first and second lead electrodes; a control component disposed above the third support member; and a conductive layer disposed underneath the first, second and third support members, wherein the first support member comprises a resin material, the second support material comprises a ceramic material and the third support member comprises a metal material.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 20, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Tomohiro Sampei
  • Patent number: 10811341
    Abstract: In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: October 20, 2020
    Assignee: Amkor Technology Singapore Holding Pte Ltd.
    Inventors: Dong Joo Park, Jin Seong Kim, Ki Wook Lee, Dae Byoung Kang, Ho Choi, Kwang Ho Kim, Jae Dong Kim, Yeon Soo Jung, Sung Hwan Cho
  • Patent number: 10685985
    Abstract: A pixel portion and a driver circuit driving the pixel portion are formed over the same substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor layer is used and a channel protective layer is provided over the oxide semiconductor layer serving as a channel formation region which is overlapped with the gate electrode. The driver circuit as well as the pixel portion is provided over the same substrate to reduce manufacturing costs.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Atsushi Umezaki
  • Patent number: 10644096
    Abstract: The frame wiring line provided in a frame region includes, at a bending section, a plurality of branch wiring lines being divided into a plurality of branches, wherein the plurality of branch wiring lines are arranged at at least two types of heights relative to a resin substrate.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: May 5, 2020
    Inventors: Masaki Yamanaka, Yohsuke Kanzaki, Takao Saitoh, Masahiko Miwa, Seiji Kaneko
  • Patent number: 10629734
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 21, 2020
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Patent number: 10622528
    Abstract: A light-emitting device includes: a resin package including: a lead part including a first lead and a second lead, each including a main body portion and a raised portion connected to the main body portion, wherein an upper surface of each of the first lead and the second lead includes a first primary surface portion in the main body portion and a curved portion in the raised portion in a cross-sectional view taken in a direction perpendicular to an upper surface of the lead part, and wherein the curved portion is continuous with and curved upward from an end portion of the first primary surface portion, a resin portion, and a recess defined by a portion of the upper surface of the lead part and the resin portion; and a light-emitting element mounted in the resin package. The curved portion is buried in the resin portion.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 14, 2020
    Inventors: Hironao Oku, Toshiyuki Hashimoto, Mitsuhiro Isono, Takao Ishihara, Takaaki Kato
  • Patent number: 10600679
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, first and second semiconductor chips disposed in the through-hole, an encapsulant encapsulating at least portions of the first connection member, the first semiconductor chip, and the second semiconductor chip, and a second connection member disposed on the first connection member and on active surfaces of the first semiconductor chip and the second semiconductor chip. A redistribution layer of the second connection member is respectively connected to both the first and second connection pads through first and second conductors, and the second conductor has a height greater than that of the first conductor.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: March 24, 2020
    Inventors: Han Kim, Mi Ja Han, Dae Hyun Park
  • Patent number: 10586923
    Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matthew N. Rocklein, D. V. Nirmal Ramaswamy
  • Patent number: 10577246
    Abstract: A carbon nanotube triode apparatus includes a plurality of Horizontally Aligned Single Wall Carbon Nano Tubes (HA-SWCNT disposed on an electrically insulating thermally conductive substrate. A first contact is disposed on the substrate and electrically coupled to a first end of the HA-SWCNT. A second contact is disposed on the substrate and separated from a second end of the HA-SWCNT by a gap. A gate terminal is coincident with a plane of the substrate.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 3, 2020
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Ahmad Ehteshamul Islam, Benji Maruyama
  • Patent number: 10573727
    Abstract: According to an embodiment of the present invention, a method for forming a semiconductor device includes pattering a first fin in a semiconductor substrate, and forming a liner layer over the first fin. The method further includes removing a first portion of the liner layer, and removing a portion of the exposed semiconductor substrate to form a first cavity. The method also includes performing an isotropic etching process to remove portions of the semiconductor substrate in the first cavity and form a first undercut region below the liner layer, growing a first epitaxial semiconductor material in the first undercut region and the first cavity, and performing a first annealing process to drive dopants from the first epitaxial semiconductor material into the first fin to form a first source/drain layer under the first fin and in portions of the semiconductor substrate.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: February 25, 2020
    Inventors: Brent A. Anderson, Huiming Bu, Fee Li Lie, Shogo Mochizuki, Junli Wang
  • Patent number: 10569197
    Abstract: A method of separating carbon nanotubes by electronic type includes centrifuging a carbon nanotube composition in contact with a first fluid medium comprising a first density gradient; and separating the carbon nanotube composition into two or more separation fractions. The carbon nanotube composition comprises two or more non-ionic amphiphilic surface active components and a carbon nanotube population comprising double-walled carbon nanotubes having a semiconducting outer wall (s-DWCNTs), and double-walled carbon nanotubes having a metallic outer wall (m-DWCNTs). The two or more separation fractions comprise a first separation fraction comprising a carbon nanotube subpopulation comprising a higher percentage of s-DWCNTs than the carbon nanotube population, and a second separation fraction comprising a carbon nanotube subpopulation comprising a higher percentage of m-DWCNTs than the carbon nanotube population.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: February 25, 2020
    Inventors: Alexander A. Green, Mark C. Hersam
  • Patent number: 10573721
    Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John Hopkins, Darwin Franseda Fan
  • Patent number: 10566574
    Abstract: An organic light emitting diode includes an anodic conductive layer, an organic EL layer, and a cathodic conductive layer formed from Ag or an alloy of Ag, or the like, sequentially laminated on a substrate, such that a two-dimensional lattice structure is provided on a surface of the cathodic conductive layer on an organic EL layer side, an extraction wavelength and a distance between centers of concave portions or convex portions in the two-dimensional lattice structure are within a region surrounded by specific coordinates in a graph illustrating a relationship between the light extraction wavelength and the distance, and the depth of the concave portions or a height of the convex portions is 12 nm to 180 nm.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: February 18, 2020
    Assignee: Oji Holdings Corporation
    Inventors: Kei Shinotsuka, Takayuki Okamoto
  • Patent number: 10553692
    Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong-Soo Kim, Sung-Won Lim, Eun-Jeong Kim, Hyun-Jin Chang, Keun Heo, Jee-Hyun Kim
  • Patent number: 10553820
    Abstract: An encapsulation method and encapsulation structure of an organic light emitting diode (OLED) are provided. The method includes: preparing an OLED substrate, the OLED substrate comprises a base substrate and at least one OLED device formed on the base substrate; forming a first encapsulation layer at a side of the OLED substrate formed with the OLED device to cover the OLED device; and forming a second encapsulation layer on the first encapsulation layer, the second encapsulation layer is a metal layer.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: February 4, 2020
    Assignees: BOE Technology Group Co., Ltd., Hefei BOE Optoelectronics Technology Co., Ltd.
    Inventors: Yajun Li, Jun Zhang
  • Patent number: 10553708
    Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 10535655
    Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ali Keshavarzi, Ta-Pen Guo, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu, Chung-Cheng Wu, Li-Chun Tien, Jung-Chan Yang, Ting-Yu Chen, Min Cao, Yung-Chin Hou
  • Patent number: 10527903
    Abstract: A structure for preventing deteriorations of a light-emitting device and retaining sufficient capacitor elements (condenser) required by each pixel is provided. A first passivation film, a second metal layer, a flattening film, a barrier film, and a third metal layer are stacked in this order over a transistor. A side face of a first opening provided with the flattening film is covered by the barrier film, a second opening is formed inside the first opening, and a third metal layer is connected to a semiconductor via the first opening and the second opening. A capacitor element that is formed of a lamination of a semiconductor of a transistor, a gate insulating film, a gate electrode, the first passivation film, and the second metal layer is provided.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 7, 2020
    Inventors: Shunpei Yamazaki, Toru Takayama, Satoshi Murakami, Hajime Kimura
  • Patent number: 10529866
    Abstract: An SOI or PSOI device including a device structure having a plurality of doped semiconductor regions. One or more of the doped semiconductor regions is in electrical communication with one or more electrical terminals. The device further includes an insulator layer located between a bottom surface of the device structure and a handle wafer. The device has an insulator trench structure located between a side surface of the device structure and a lateral semiconductor region located laterally with respect to the device structure. The insulator layer and the insulator trench structure are configured to insulate the device structure from the handle wafer and the lateral semiconductor region, and the insulator trench structure includes a plurality of insulator trenches.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: January 7, 2020
    Inventors: Elizabeth Kho Ching Tee, Alexander Dietrich Holke, Steven John Pilkington, Deb Kumar Pal
  • Patent number: 10529948
    Abstract: An organic EL display device includes a base substrate, an organic EL element provided on the base substrate and including a plurality of organic EL layers arranged in a matrix form, a sealing film provided on the organic EL element, and a plurality of sub pixels defined corresponding to the plurality of organic EL layers. The sealing film is provided with a groove formed to run between adjacent ones of the plurality of sub pixels.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 7, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Sonoda, Takashi Ochi, Hisao Ochi, Tohru Senoo, Takeshi Hirase, Akihiro Matsui, Jumpei Takahashi