Abstract: A display panel includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a display element located in the second region and including a pixel electrode, an opposite electrode, an intermediate layer; a multi-layered film arranged between the substrate and the pixel electrode and including an organic insulating layer and an inorganic layer on the organic insulating layer; and at least one groove formed in the multi-layered film and located in the third region, wherein at least one organic material layer is included in the intermediate layer and is disconnected by the at least one groove.

Abstract: Provided is a display substrate, which includes a base substrate, a circuit structure layer disposed on the base substrate, multiple ultrasonic sensing elements and multiple micro light-emitting elements. The multiple ultrasonic sensing elements are disposed on a side of the circuit structure layer away from the base substrate, and are electrically connected to the circuit structure layer, and the multiple light-emitting elements are disposed on the side of the circuit structure layer away from the base substrate, and are electrically connected to the circuit structure layer. An orthographic projection of the multiple ultrasonic sensing elements on the base substrate does not overlap with an orthographic projection of the multiple micro light-emitting elements on the base substrate.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes following operations. A substrate including active regions and isolation regions is provided. First trench structures are formed on the substrate, the first trench structure passing through the active region and the isolation region. Bit line contact structures are formed in the first trench structures. Bit line structures are formed on the bit line contact structures, at least part of the bit line structure being positioned in the first trench structure. Bit line protection structures are formed on the bit line structures, the bit line protection structure at least covering an upper surface of the bit line structure. Capacitor contact assemblies are formed, the capacitor contact assembly including a first capacitor contact structure and a second capacitor contact structure which covers an upper surface and part of a side wall of the first capacitor contact structure.

Abstract: A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

Abstract: Systems, methods and apparatus are provided for decoupling capacitors for an array of vertically stacked memory cells. Embodiments provide that the decoupling capacitors are electrically coupled to a power bus.

Abstract: A self-luminous display panel is provided. The self-luminous display panel includes a power supply film layer. The power supply film layer is divided into a plurality of mutually insulated power supply blocks, and each power supply block is electrically connected to a plurality of pixel circuits located in the power supply block. A high grayscale display is independently provided for the corresponding pixel circuits by dividing the power supply film into power supply blocks, thereby easily achieving the partition display of the self-luminous display panel.

Abstract: An electroluminescence display device can include a substrate having a display area and a non-display area adjacent with the display area, where the display area includes a plurality of pixels for displaying images. The display device can further include a thin film transistor on the substrate, a light emitting diode electrically connected with the thin film transistor and including a pixel driving electrode, a light emitting layer and a common electrode. The display device can further include an encapsulation layer disposed on the light emitting diode, where the encapsulation layer can include a first inorganic layer, a second inorganic layer on the first inorganic layer, and an organic layer between the first inorganic layer and the second inorganic layer. The display device can further include a through-hole disposed in the display area and penetrating the substrate and the encapsulation layer.

Abstract: A layout method includes: generating a design data including an electronic circuit; and generating a design layout by placing a cell corresponding to the electronic circuit. The cell includes a first transistor and a second transistor over the first transistor. The first transistor includes a gate extending in a first direction, a first active region arranged in a first layer and extending in a second direction, and a first conductive line and a second conductive line arranged on two sides of the first active region. The second transistor includes the gate, a second active region arranged in a second layer over the first layer and extending in the second direction, and a third conductive line and a fourth conductive line arranged on two sides of the second active region. At least one of the four conductive lines includes a first portion non-overlapped with the gate in the first direction.

Abstract: A process for mounting a light component on a carrier. The light component includes a generally planar substrate, on a first face of which submillimetre-sized electroluminescent semiconductor elements are epitaxied in the form of a matrix. The process is noteworthy in that it eliminates the need for a layer of filler material between the component and the carrier, while providing good thermal and electrical conductivity between the component and the carrier and high mechanical strength.

Abstract: Provided is a manufacturing method of an electronic device, including forming a circuit layer on a base layer, disposing a light emitting element for attachment over the circuit layer, disposing an insulating layer between the light emitting element and the circuit layer, and drying the insulation layer to attach the light emitting element with the insulating layer and the circuit layer.

Abstract: FinFET structures and methods of forming the same are disclosed. In a method, a fin is formed on a substrate, an isolation region is formed on opposing sides of the fin. The isolation region is doped with carbon to form a doped region, and a portion of the isolation region is removed to expose a top portion of the fin, wherein the removed portion of the isolation region includes at least a portion of the doped region.

Abstract: A heat radiation member excellent in electrical insulation and better in thermal conduction is provided. The heat radiation member includes a substrate composed of a composite material containing diamond and a metallic phase, an insulating plate provided on at least a part of front and rear surfaces of the substrate and composed of an aluminum nitride, and a single bonding layer interposed between the substrate and the insulating plate, the heat radiation member having thermal conductivity not lower than 400 W/m·K.

Abstract: Provided are a thermal conductive silicone composition having a favorable heat dissipation property; and a semiconductor device using such composition. The thermal conductive silicone composition contains: (A) an organopolysiloxane that has a kinetic viscosity of 10 to 100,000 mm2/s at 25° C., and is represented by the following average composition formula (1) R1aSiO(4-a)/2??(1) wherein R1 represents a hydrogen atom, a saturated or unsaturated monovalent hydrocarbon group having 1 to 18 carbon atoms or a hydroxy group, and a represents a number satisfying 1.8?a?2.2; (B) a silver powder having a tap density of not lower than 3.0 g/cm3, a specific surface area of not larger than 2.0 m2/g and an aspect ratio of 1 to 30; (C) an elemental gallium and/or gallium alloy having a melting point of 0 to 70° C. and being present at a mass ratio [Component (C)/{Component (B)+Component (C)}] of 0.001 to 0.1; and (D) a catalyst.

Abstract: A display panel includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a display element located in the second region and including a pixel electrode, an opposite electrode, an intermediate layer; a multi-layered film arranged between the substrate and the pixel electrode and including an organic insulating layer and an inorganic layer on the organic insulating layer; and at least one groove formed in the multi-layered film and located in the third region, wherein at least one organic material layer is included in the intermediate layer and is disconnected by the at least one groove.

Abstract: A wafer lens array includes a wafer lens formed by arranging a plurality of plate members on a plane, each plate member including a first window configured to allow light for forming an optical image to pass through, a first light-shielding portion formed on an outer circumference of the first window and a second window formed on an outer circumferential side of the first light-shielding portion and configured to allow illumination light to pass through, and the wafer lens in plurality are coaxially layered and the layered wafer lenses are bonded and fixed together in a region of the second window.

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

Abstract: A semiconductor device with stable electrical characteristics is provided. Alternatively, a semiconductor device having normally-off electrical characteristics is provided. A semiconductor device includes a gate electrode, a gate insulator, and an oxide semiconductor, the oxide semiconductor contains fluorine in a channel formation region, and a fluorine concentration in the channel formation region is higher than or equal to 1×1020 atoms/cm3 and lower than or equal to 1×1022 atoms/cm3. Note that fluorine is added by an ion implantation method.

Abstract: A semiconductor device including a capacitor whose charge capacity is increased while improving the aperture ratio is provided. Further, a semiconductor device which consumes less power is provided. A transistor which includes a light-transmitting semiconductor film, a capacitor in which a dielectric film is provided between a pair of electrodes, an insulating film which is provided over the light-transmitting semiconductor film, and a first light-transmitting conductive film which is provided over the insulating film are included. The capacitor includes the first light-transmitting conductive film which serves as one electrode, the insulating film which functions as a dielectric, and a second light-transmitting conductive film which faces the first light-transmitting conductive film with the insulating film positioned therebetween and functions as the other electrode.

Abstract: Methods of fabrication and nano-sensor and nano-sensor array thereof are provided. A sensing electrode assembly can be patterned on a sacrificial layer of a substrate. The sensing electrode assembly can comprise a pair of contact pads and an electrode element coupled to and disposed between the pair of contact pads. The sensing electrode assembly can be formed on the patterned sensing electrode assembly. The sacrificial layer below a portion of the electrode element can be removed to obtain a suspended electrode element. The suspended electrode element can be oxidized at a first predetermined temperature to obtain a pair of electromigrated regions and a notch portion between the pair of the electromigrated regions. The notch portion can be used to detect a gaseous component in an ambient gas at a second predetermined temperature.

Abstract: A display panel and a display device are provided. By manufacturing a first via hole and a second via hole first, and then manufacturing a third via hole and a fourth via hole, the first via hole and the second via hole have been covered by a corresponding first drain electrode and first source electrode before performing hydrofluoric acid cleaning processes, and a first drain region and a first source region of a first oxide transistor are not affected by the hydrofluoric acid cleaning process, thereby allowing an oxide channel of the first oxide transistor to also be prevented from being affected.