Abstract: Various methods for manufacturing semiconductor structures are provided. An embodiment method includes forming a first patterned hard mask and epitaxial layer on a semiconductor substrate, and forming a first doped region in the epitaxial layer by performing a first implantation through the first patterned hard mask. A second doped region is formed in the epitaxial layer by performing a second implantation through the first patterned hard mask, with the first doped region at least partially overlapping the second doped region. A second patterned hard mask is formed, which surrounds the first patterned hard mask and covers at least a portion of the first doped region. A third doped region is formed in the epitaxial layer by performing a third implantation through the first patterned hard mask and the second patterned hard mask.

Abstract: Exemplary semiconductor processing chambers include a chamber body defining a processing region. The chambers may include a substrate support disposed within the processing region. The substrate support may have an upper surface that defines a recessed substrate seat. The chambers may include a shadow ring disposed above the substrate seat and the upper surface. The shadow ring may extend about a peripheral edge of the substrate seat. The chambers may include bevel purge openings defined within the substrate support proximate the peripheral edge. A bottom surface of the shadow ring may be spaced apart from a top surface of the upper surface to form a purge gas flow path that extends from the bevel purge openings along the shadow ring. A space formed between the shadow ring and the substrate seat may define a process gas flow path. The gas flow paths may be in fluid communication with one another.

Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.

Abstract: A display substrate and a display device. The display substrate includes: a plurality of pixel islands, a first opening, a second opening and a first passage region. Each pixel island includes at least one pixel, each pixel includes a plurality of first driving lines, the first passage region is provided with a plurality of first connection lines, each of the plurality of pixel islands further includes a plurality of transfer lines, and the plurality of transfer lines are arranged in different layers from the plurality of first driving lines and cross each other to form a plurality of overlapping regions; the plurality of transfer lines are electrically connected with the plurality of first driving lines through via holes located in part of the overlapping regions, and the transfer lines in two adjacent pixel islands are respectively connected with the plurality of first connection lines in the first passage region.

Abstract: Transistors using nitride semiconductor layers as channels were experimentally manufactured. The nitride semiconductor layers were all formed through a sputtering method. A deposition temperature was set at less than 600° C., and a polycrystalline or amorphous InxGayAlzN layer was obtained. When composition expressed with a general expression InxGayAlzN (where x+y+z=1.0) falls within a range of 0.3?x?1.0 and 0?z<0.4, a transistor 1a exhibiting an ON/OFF ratio of 102 or higher can be obtained. That is, even a polycrystalline or amorphous film exhibits electric characteristics equal to those of a single crystal. Therefore, it is possible to provide a semiconductor device in which constraints to manufacturing conditions are drastically eliminated, and which includes an InGaAlN-based nitride semiconductor layer which is inexpensive and has excellent electric characteristics as a channel.

Abstract: Provided is a display substrate, which includes a base substrate, a circuit structure layer disposed on the base substrate, multiple ultrasonic sensing elements and multiple micro light-emitting elements. The multiple ultrasonic sensing elements are disposed on a side of the circuit structure layer away from the base substrate, and are electrically connected to the circuit structure layer, and the multiple light-emitting elements are disposed on the side of the circuit structure layer away from the base substrate, and are electrically connected to the circuit structure layer. An orthographic projection of the multiple ultrasonic sensing elements on the base substrate does not overlap with an orthographic projection of the multiple micro light-emitting elements on the base substrate.

Abstract: A display panel includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a display element located in the second region and including a pixel electrode, an opposite electrode, an intermediate layer; a multi-layered film arranged between the substrate and the pixel electrode and including an organic insulating layer and an inorganic layer on the organic insulating layer; and at least one groove formed in the multi-layered film and located in the third region, wherein at least one organic material layer is included in the intermediate layer and is disconnected by the at least one groove.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes following operations. A substrate including active regions and isolation regions is provided. First trench structures are formed on the substrate, the first trench structure passing through the active region and the isolation region. Bit line contact structures are formed in the first trench structures. Bit line structures are formed on the bit line contact structures, at least part of the bit line structure being positioned in the first trench structure. Bit line protection structures are formed on the bit line structures, the bit line protection structure at least covering an upper surface of the bit line structure. Capacitor contact assemblies are formed, the capacitor contact assembly including a first capacitor contact structure and a second capacitor contact structure which covers an upper surface and part of a side wall of the first capacitor contact structure.

Abstract: A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

Abstract: A self-luminous display panel is provided. The self-luminous display panel includes a power supply film layer. The power supply film layer is divided into a plurality of mutually insulated power supply blocks, and each power supply block is electrically connected to a plurality of pixel circuits located in the power supply block. A high grayscale display is independently provided for the corresponding pixel circuits by dividing the power supply film into power supply blocks, thereby easily achieving the partition display of the self-luminous display panel.

Abstract: Systems, methods and apparatus are provided for decoupling capacitors for an array of vertically stacked memory cells. Embodiments provide that the decoupling capacitors are electrically coupled to a power bus.

Abstract: An electroluminescence display device can include a substrate having a display area and a non-display area adjacent with the display area, where the display area includes a plurality of pixels for displaying images. The display device can further include a thin film transistor on the substrate, a light emitting diode electrically connected with the thin film transistor and including a pixel driving electrode, a light emitting layer and a common electrode. The display device can further include an encapsulation layer disposed on the light emitting diode, where the encapsulation layer can include a first inorganic layer, a second inorganic layer on the first inorganic layer, and an organic layer between the first inorganic layer and the second inorganic layer. The display device can further include a through-hole disposed in the display area and penetrating the substrate and the encapsulation layer.

Abstract: A layout method includes: generating a design data including an electronic circuit; and generating a design layout by placing a cell corresponding to the electronic circuit. The cell includes a first transistor and a second transistor over the first transistor. The first transistor includes a gate extending in a first direction, a first active region arranged in a first layer and extending in a second direction, and a first conductive line and a second conductive line arranged on two sides of the first active region. The second transistor includes the gate, a second active region arranged in a second layer over the first layer and extending in the second direction, and a third conductive line and a fourth conductive line arranged on two sides of the second active region. At least one of the four conductive lines includes a first portion non-overlapped with the gate in the first direction.

Abstract: A process for mounting a light component on a carrier. The light component includes a generally planar substrate, on a first face of which submillimetre-sized electroluminescent semiconductor elements are epitaxied in the form of a matrix. The process is noteworthy in that it eliminates the need for a layer of filler material between the component and the carrier, while providing good thermal and electrical conductivity between the component and the carrier and high mechanical strength.

Abstract: Provided is a manufacturing method of an electronic device, including forming a circuit layer on a base layer, disposing a light emitting element for attachment over the circuit layer, disposing an insulating layer between the light emitting element and the circuit layer, and drying the insulation layer to attach the light emitting element with the insulating layer and the circuit layer.

Abstract: FinFET structures and methods of forming the same are disclosed. In a method, a fin is formed on a substrate, an isolation region is formed on opposing sides of the fin. The isolation region is doped with carbon to form a doped region, and a portion of the isolation region is removed to expose a top portion of the fin, wherein the removed portion of the isolation region includes at least a portion of the doped region.

Abstract: A heat radiation member excellent in electrical insulation and better in thermal conduction is provided. The heat radiation member includes a substrate composed of a composite material containing diamond and a metallic phase, an insulating plate provided on at least a part of front and rear surfaces of the substrate and composed of an aluminum nitride, and a single bonding layer interposed between the substrate and the insulating plate, the heat radiation member having thermal conductivity not lower than 400 W/m·K.

Abstract: Provided are a thermal conductive silicone composition having a favorable heat dissipation property; and a semiconductor device using such composition. The thermal conductive silicone composition contains: (A) an organopolysiloxane that has a kinetic viscosity of 10 to 100,000 mm2/s at 25° C., and is represented by the following average composition formula (1) R1aSiO(4-a)/2??(1) wherein R1 represents a hydrogen atom, a saturated or unsaturated monovalent hydrocarbon group having 1 to 18 carbon atoms or a hydroxy group, and a represents a number satisfying 1.8?a?2.2; (B) a silver powder having a tap density of not lower than 3.0 g/cm3, a specific surface area of not larger than 2.0 m2/g and an aspect ratio of 1 to 30; (C) an elemental gallium and/or gallium alloy having a melting point of 0 to 70° C. and being present at a mass ratio [Component (C)/{Component (B)+Component (C)}] of 0.001 to 0.1; and (D) a catalyst.

Abstract: A display panel includes: a substrate including a first region, a second region, and a third region between the first region and the second region; a display element located in the second region and including a pixel electrode, an opposite electrode, an intermediate layer; a multi-layered film arranged between the substrate and the pixel electrode and including an organic insulating layer and an inorganic layer on the organic insulating layer; and at least one groove formed in the multi-layered film and located in the third region, wherein at least one organic material layer is included in the intermediate layer and is disconnected by the at least one groove.

Abstract: A wafer lens array includes a wafer lens formed by arranging a plurality of plate members on a plane, each plate member including a first window configured to allow light for forming an optical image to pass through, a first light-shielding portion formed on an outer circumference of the first window and a second window formed on an outer circumferential side of the first light-shielding portion and configured to allow illumination light to pass through, and the wafer lens in plurality are coaxially layered and the layered wafer lenses are bonded and fixed together in a region of the second window.