Patents Examined by Ori Nadav
  • Patent number: 10529866
    Abstract: An SOI or PSOI device including a device structure having a plurality of doped semiconductor regions. One or more of the doped semiconductor regions is in electrical communication with one or more electrical terminals. The device further includes an insulator layer located between a bottom surface of the device structure and a handle wafer. The device has an insulator trench structure located between a side surface of the device structure and a lateral semiconductor region located laterally with respect to the device structure. The insulator layer and the insulator trench structure are configured to insulate the device structure from the handle wafer and the lateral semiconductor region, and the insulator trench structure includes a plurality of insulator trenches.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: January 7, 2020
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES GMBH
    Inventors: Elizabeth Kho Ching Tee, Alexander Dietrich Holke, Steven John Pilkington, Deb Kumar Pal
  • Patent number: 10529948
    Abstract: An organic EL display device includes a base substrate, an organic EL element provided on the base substrate and including a plurality of organic EL layers arranged in a matrix form, a sealing film provided on the organic EL element, and a plurality of sub pixels defined corresponding to the plurality of organic EL layers. The sealing film is provided with a groove formed to run between adjacent ones of the plurality of sub pixels.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: January 7, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Sonoda, Takashi Ochi, Hisao Ochi, Tohru Senoo, Takeshi Hirase, Akihiro Matsui, Jumpei Takahashi
  • Patent number: 10515987
    Abstract: A thin film transistor array substrate includes: a substrate on which a thin film transistor and a storage capacitor are formed. The storage capacitor includes a first electrode plate formed on the substrate, a gate isolation layer or an etching stopper layer formed on the first electrode plate, and a second electrode plate formed on the gate isolation layer or the etching stopper layer. The etching stopper layer may be formed on the gate isolation layer, of which one is partially etched and removed such that there is only one of the gate isolation layer and the etching stopper layer existing between the two electrode plates of the storage capacitor so as to reduce the overall thickness of the isolation layer of the storage capacitor. Thus, the capacitor occupies a smaller area and a higher aperture ratio may be achieved.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 24, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaowen Lv
  • Patent number: 10510790
    Abstract: A circuit structure includes a semiconductor substrate having a top surface. A dielectric material extends from the top surface into the semiconductor substrate. A high-k dielectric layer is formed of a high-k dielectric material, wherein the high-k dielectric layer comprises a first portion on a sidewall of the dielectric material, and a second portion underlying the dielectric material.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 10510581
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 10509286
    Abstract: A manufacturing method of the invention, comprising: successively forming an insulation layer and a photoresist layer on a transparent substrate; performing an exposure and a development on the photoresist layer by a back exposure process, so as to form a trench in the photoresist layer, an open area of the trench proximal to the insulation layer is larger than that of the trench distal to the insulation layer; removing a portion of insulation material in a region of the insulation layer exposed through the trench by an etching process, so as to form a slot in the insulation layer; forming a metal layer on a side of the photoresist layer distal to the insulation layer, a portion of the metal layer is embedded in the slot; removing the photoresist layer and the metal layer thereon by a stripping process, and retaining the portion of the metal layer in the slot.
    Type: Grant
    Filed: October 9, 2016
    Date of Patent: December 17, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yunhai Wan, Chengshao Yang, Ling Han, Botao Song
  • Patent number: 10505083
    Abstract: Methods for fabricating a semiconductor devices, and in particular light emitting diodes (LEDS) comprising providing a plurality of semiconductor devices on a substrate and forming a contact on at least some of the semiconductor devices. A containment structure is formed on at least some of the semiconductor devices having a contact with each containment structure defining a deposition area excluding the contact. A coating material is deposited then within the deposition area, with the coating material not covering the contact. A light emitting diode (LED) chip wafer comprising a plurality of LEDs on a substrate wafer with at least some of the LEDs having a contact. A plurality of containment structures are included, each of which is associated with a respective one of the plurality of LEDs. Each of the containment structures at least partially on its respective one of the LEDs and defining a deposition area on its respective one of the LEDs. The deposition area excludes the contact.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: December 10, 2019
    Assignee: CREE, INC.
    Inventors: James Ibbetson, Kristi Wong, Maryanne Becerra
  • Patent number: 10506345
    Abstract: According to an embodiment, a microfabricated structure includes a cavity disposed in a substrate, a first clamping layer overlying the substrate, a deflectable membrane overlying the first clamping layer, and a second clamping layer overlying the deflectable membrane. A portion of the second clamping layer overlaps the cavity.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: December 10, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Wolfgang Klein, Reinhard Gabl
  • Patent number: 10497560
    Abstract: Some embodiments of the present disclosure relate to a method for forming flash memory. In this method, a tunnel oxide is formed over a semiconductor substrate. A layer of silicon dot nucleates is formed on the tunnel oxide. The layer of silicon dots includes silicon dot nucleates having respective initial sizes which differ according to a first size distribution. An etching process is performed to reduce the initial sizes of the silicon dot nucleates so reduced-size silicon dot nucleates have respective reduced sizes which differ according to a second size distribution. The second size distribution has a smaller spread than the first size distribution.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Tsu-Hui Su, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 10453953
    Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 22, 2019
    Assignee: VISHAY-SILICONIX
    Inventors: Kyle Terrill, Yuming Bai, Deva Pattanayak, Zhiyun Luo
  • Patent number: 10446647
    Abstract: A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: October 15, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10446608
    Abstract: A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 15, 2019
    Assignee: NXP USA, INC.
    Inventor: Anirban Roy
  • Patent number: 10431675
    Abstract: A carbon nanotube triode apparatus includes a plurality of Horizontally Aligned Single Wall Carbon Nano Tubes (HA-SWCNT) disposed on an electrically insulating thermally conductive substrate. A first contact is disposed on the substrate and electrically coupled to a first end of the HA-SWCNT. A second contact is disposed on the substrate and separated from a second end of the HA-SWCNT by a gap. A gate terminal is coincident with a plane of the substrate.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: October 1, 2019
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Ahmad Ehteshamul Islam, Benji Maruyama
  • Patent number: 10418439
    Abstract: At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: September 17, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig-Guitart, Peter Moens, Zia Hossain
  • Patent number: 10411137
    Abstract: Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: September 10, 2019
    Assignee: ABLIC Inc.
    Inventor: Tomomitsu Risaki
  • Patent number: 10411086
    Abstract: In accordance with an embodiment, a method of manufacturing an electrical component that may include a high voltage capacitor that includes providing a semiconductor material of a second conductivity type in which first doped region of a first conductivity type is formed. A plurality of doped regions of the first conductivity type and a plurality of doped regions of the second conductivity type are formed in the first doped region. A first p-n junction is formed between first doped regions of the first and second conductivity types and a second p-n junction is formed between second doped regions of the first and second conductivity types. A metallization system is formed above the doped regions so that capacitors are formed by a parallel connection of a first metal layer to a polysilicon layer and the first metal layer to a second metal layer.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: September 10, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Richard Scott Burton, Karel Ptacek
  • Patent number: 10403498
    Abstract: The present invention pertains to a group III-V compound semiconductor nanowire able to be used in a group III-V compound semiconductor MOSFET (FET) operational at a small subthreshold (100 mV/dec or less). A side face of the group III-V compound semiconductor nanowire is a (?110) plane constituted of a very small (111) plane. The group III-V compound semiconductor nanowire has, e.g., a first layer having a (111)A plane as a side face thereof, and a second layer having a (111)B plane as a side face thereof. The first layer and the second layer are stacked alternatingly in the axial direction.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: September 3, 2019
    Assignees: NATIONAL UNIVERSITY CORPORATION HAKKAIDO UNIVERSITY, JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Takashi Fukui, Katsuhiro Tomioka
  • Patent number: 10403716
    Abstract: A method is presented for forming a semiconductor device. The method includes forming source/drain over a semiconductor substrate, forming a sacrificial layer over the source/drain, and forming an inter-level dielectric (ILD) layer over the sacrificial layer. The method further includes forming trenches that extend partially into the sacrificial layer, removing the sacrificial layer to expose an upper surface of the source/drain, and filling the trenches with at least one conducting material. The sacrificial layer is germanium (Ge) and the at least one conducting material includes three conducting materials.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 3, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 10396000
    Abstract: Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: August 27, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Tenko Yamashita, Chun-Chen Yeh, Hui Zang
  • Patent number: 10388563
    Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rak Hwan Kim, Byung Hee Kim, Sang Bom Kang, Jong Jin Lee, Eun Ji Jung