Abstract: A plurality of unsingulated dies on a wafer may be individually powered up using various "electronic mechanisms" on the wafer, and connecting the electronic mechanisms to the individual dies by conductive lines on the wafer. The electronic mechanisms are capable of powering-up a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively power up the dies.

Abstract: A number of dielectrically isolated single crystal islands are formed by implanting neon or other group Zero ions into a semiconductor substrate, preferably silicon, at a sufficiently high energy to created an amorphized region in the interior of the substrate, without excessively damaging the substrate surface through which the ions pass. The amorphized regions are highly resistive, and are suitable for isolation in some applications. Where better isolation is desired, a dielectric isolation structure is formed as follows. Trenches are formed down into the amorphized regions, and the substrate is heavily oxidized to convert the amorphized regions into buried oxide regions and the island sidewalls into oxide. The islands are made thicker by removing the oxide from the islands' top surfaces and sidewalls, and growing epitaxial silicon over the substrate. Second trenches are formed down to the buried oxide regions, and the substrate is again oxidized to convert the islands' sidewalls to oxide.

Abstract: A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable fur a capacitor electrode because of its increased effective surface area.

Abstract: A method of manufacturing a device, preferably a semiconductor device, whereby a mask (3) with an opening (4) extending down to a bare body (1) is provided on a surface (2) of this body (1), after which a substance (5) is implanted into the body (1) through the opening (4), upon which the mask (3) is removed. The mask (3) is provided by depositing a first and a second layer (6, 7, respectively) on the surface (2), and these layers are provided with the opening (4), while the first layer (6) can be selectively removed relative to the material of the body (1), and the second layer (7) is of the same material as the body (1). Since the same material is used for the second layer (7) as for the body (1), the body (1) is not polluted with material from the mask (3) in the opening (4) during implantation.

Abstract: An apparatus (40) for providing consistent, non-jamming registration of a semiconductor wafer (46) undergoing process work includes a plate (42) upon which the wafer (46) is laid flat. A flat (45) of the wafer (46) is registered against two rollers (43') that are fixedly mounted to the plate (42). A third roller (43), also fixedly mounted to the plate (42), registers a first point (47) along the circumference of the wafer (46). A fourth roller (48) is fixedly mounted to a bracket (50) that is movable approximately along the radius of the wafer (46). A force (54) is applied to this bracket (50) resulting in the fourth roller (48) applying a force against the wafer (46). This resultant force, coupled with the rotating capability of the rollers (43, 43', 48), allows the wafer (46) to rotate into a proper registration position. A second embodiment (60) that incorporates essentially these same force and rotation dynamics through the use of flexures (64, 66, 68) is also disclosed.

Abstract: Disclosed is a process for fabricating mixed crystals and, in particular, III-V semiconductors, in which at least one component of the composition of the mixed crystal is transferred in a reactor from a source into a vapor phase containing hydrogen and chloride compounds as well as a carrier gas and mixed with said component or other components of said composition of said mixed crystal, transported to a substrate and precipitated on said substrate. The invented process is distinguished in that in order to vary the growth rate between approximately 1 <m/h and approximately 500 <m/h, the overall pressure is varied between approximately 80 mbar and approximately 1 mbar.

Abstract: A method is provided for forming a polycrystalline silicon resistive load element of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A lightly doped first conductive layer having a conductivity of a first type. A first oxide layer is formed over the integrated circuit with a first opening therethrough exposing a portion of the first conductive layer. Using the first oxide layer as a mask, the exposed portion of the first conductive layer is then implanted with a dopant of a second conductivity type to form a junction between the exposed portion and the portion covered by the mask. A second oxide region is then formed on a portion of the first oxide layer in the first opening, over the junction and over a portion of the exposed first conductive layer adjacent to the junction. A silicide is formed over the exposed portion of the first conductive layer.

Abstract: The metallization of the back of the semiconductor substrate is obtained by depositing a series of metal layers, after ion implantation of dopant on the interface with the first layer. The step of ion implantation is followed by the deposition of one or more metal layers of the aforesaid series, and then by thermal annealing under vacuum or in an inert atmosphere, at a temperature considerably lower than 500.degree. C. and for a period considerably shorter than 60 minutes.

Abstract: A method of removing from a stainless steel surface a difficultly removable soil originating from an animal or vegetable source comprising the step of contacting the soil adhered to the surface with an amount of a noncorrosive chemical composition effective to ultimately essentially chemically remove the soil from at least 51% of the surface. The difficultly removable soils that can be removed by the method of the invention are otherwise ultimately essentially chemically removable from at least 51% of the surface, at the temperature at which the above contacting step is conducted, only by contact with at least one corrosive chemical composition. The method is both safe for the user and highly effective to remove the above-described soils.

Abstract: A unipolar electronic component is proposed with a quasi one dimensional carrier channel which has all the characteristics of an FET. This component can be very simply produced, has "self-alignment" and linear gates with a low capacity in place of planar gates. In this way a very high operating frequency of the component is possible. The structure comprises an initially homogenous 2D-layer with a high carrier mobility which is formed by epitaxy of for example GaAs. The implantation of focussed ions (for example Ga.sup.+ with 100 keV) locally destroys the conductivity of the electron layer. The irradiated regions remain insulating at low temperature or room temperature even after illuminating the cristal with bandgap radiation. The writing in of the insulating layer is carried out along two paths on the chip so that the 2D-carrier layer is subdivided into three regions insulated from one another.

Abstract: A semiconductor memory cell with parallel gates is disclosed. The direction of the gates is desirably chosen to minimize lithographic astigmatic effects. Thus gates of comparatively uniform width are produced and predictability of transistor performance thereby improved. Another embodiment of the invention features a connection between two conductive layers and a source/drain. The connection forms a node between one access transistor and one pull-down transistor.

Abstract: This invention is a vapor-phase process for cleaning metal-containing contaminants from the surfaces of integrated circuits and semiconductors between the numerous fabricating steps required to manufacture the finished electronic devices. The process employs cleaning agents comprising an effective amount of hexamethyldisilazane. The process comprises contacting the surface to be cleaned with an effective amount of the desired cleaning agent at a temperature sufficient to form volatile metal-ligand complexes on the surface of the substrate to be cleaned. The volatile metal-ligand complexes are sublimed from the surfaces of the substrate providing a clean, substantially residue-free surface.

Abstract: Local Encroachment Reduction (LER) is described, in which a fraction of field oxide is selectively etched. A high energy boron implant is used to maintain adequate active area isolation after the removal. This implant also doubles as a LER high capacitance and provides a carrier to minority substrate electrons. After the high energy boron implant, an N-type bottom plate capacitor is implanted. At that point, the wafer is completed by existing techniques.

Abstract: Disclosed are methods and apparatuses for improved etching of semiconductor wafers and the like using hydrofluoric acid (HF) and water mixtures or solutions which generate equilibrium vapor mixtures of HF vapor and water vapor which serve as a homogenous etchant gas. The vapor etchants do not employ a carrier gas which will make the vapors nonhomogeneous and reduce etching rates. The vapors are preferably generated from a liquid source which is provided within a contained reaction chamber which holds the wafer. The wafer is preferably oriented with the surface being processed directed downward. The wafer is advantageously positioned above or in close proximity to the equilibrium liquid source of the vapor. The wafer is rotated at a rotational speed in the range of 20-1000 revolutions per minute to provide uniform dispersion of the homogeneous etchant gas across the wafer surface and to facilitate circulation and transfer from the liquid source into etchant gas and onto the processed surface.

Abstract: A process for forming an Al film of good quality according to the CVD method utilizing the reaction between alkyl aluminum hydride and hydrogen, which is an excellent deposited film formation process also capable of selective deposition of Al.

Abstract: A manufacturing process for a semiconductor device comprising the following steps: to spin-coat by Spin-on method a solution for forming a SOG film on a wafer having a device formed on the surface to form a coating of the SOG film forming solute thereon; to treat by a liquid which is able to dissolve the solute for forming SOG film at least a part of the wafer which is held by claws of a dry etching system at a later stage in the series of processes, thereby removing a coating of the SOG film forming solute at that part; and to then bake the wafer to complete a SOG film.

Abstract: An instrument for forming nanometric features on surfaces of materials having a motor driven support for moving a workpiece on an X-Y-Z axis, a scribing tool of nanometric proportion engagable with the workpiece and a laser system for sensing movement. The tool is mounted on piezoelectric actuating means and the entire system is under the control of a programmed computer processing unit.

Abstract: Semiconductor diamond is formed by a process comprising irradiating diamond crystal with light having irradiation density of more than 0.1 W/cm.sup.2, annihilating defects in the diamond crystals, and cleaning the surface of the diamond crystals.

Abstract: A method of forming a buried contact to a source/drain junction or other active device region in a silicon substrate. A silicon oxide layer is formed over the silicon substrate. A first polysilicon layer is formed over the silicon oxide layer. A resist mask having an opening over the planned said buried contact is formed and the first polysilicon layer is isotropically etched to form a tapered opening to said underlying silicon oxide which opening undercuts the resist mask. The silicon oxide layer is anisotropically etched using the same resist mask which results in an opening to the silicon substrate corresponding to the resist pattern opening while leaving a silicon oxide border uncovered with the first polysilicon layer. A second polysilicon layer is deposited over the first polysilicon layer, the opening to the silicon substrate and the border of uncovered silicon oxide. The planned buried contact region is covered with a resist mask.

Abstract: The invention pertains to a transport system for transporting containers or products within and along an essentially vertical tube with concurrent rotation of the containers on the axis of the tube. In order to facilitate simple construction despite conditions of limited space, it is proposed that the tube be designed as a vertical rotary tube, to which a rotatably retained worm sleeve is connected at the end of the transport path. Provided within the rotary tube are longitudinal guide grooves, in which dogs carried by the containers engage. These dogs also engage in the screw thread of the worm sleeve. On their upper and lower sides, the containers have couplings, e.g., an end toothing, which, during the transport of a group of adjoining containers, impart a rotary movement from container to container but also make possible a separation of one container from another in the direction of the axis of the tube.