Patents Examined by Ourmazd S. Ojan
  • Patent number: 5316970
    Abstract: Ionization of air without the use of corona discharge tips, thereby to avoid the generation of particulates from corrosion of the corona tips, is accomplished by use of a laser beam focussed to a small focal volume of intense electric field adjacent a semiconductor chip. The electric field is sufficiently intense to ionize air. In the manufacture of a semiconductor circuit chip, during those steps which are conducted in an air environment, opportunity exists to remove from a surface of a chip, or wafer, charge acquired during the manufacturing process. The ionized air is passed along the chip surface. Ions in the air discharge local regions of the chip surface which have become charged by steps of a manufacturing process. By way of further embodiment of the invention, the ionization may be produced by injection of molecules of water into the air, which molecules are subsequently ionized by a laser beam and directed toward the chip via a light shield with the aid of a magnetic field.
    Type: Grant
    Filed: June 5, 1992
    Date of Patent: May 31, 1994
    Assignee: International Business Machines Corporation
    Inventors: John S. Batchelder, Vaughn P. Gross, Robert A. Gruver, Philip C. D. Hobbs, Kenneth D. Murray
  • Patent number: 5316972
    Abstract: In forming a deposited film composed mainly of Al according to the CVD method utilizing gas of alkyl aluminum hydride, hydrogen gas, and if desired, further gas containing Si atoms, film formation is carried out by shifting the deposition rate from a low deposition rate to a high deposition rate.According to this method, excellent selectivity is exhibited and also a film excellent in flatness can be deposited at a high deposition rate.
    Type: Grant
    Filed: June 17, 1992
    Date of Patent: May 31, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuo Mikoshiba, Kazuo Tsubouchi, Kazuya Masu
  • Patent number: 5314832
    Abstract: A process for the production of a high voltage, MIS integrated circuit or a substrate incorporating double implantation MIS transistors creates transistors whose sources and drains consist of double junctions and whose gates are formed in a semiconducting layer. The initial process includes a first implantation of ions of a given conductivity type in the substrate and at a given dose, in order to form there the first source and drain junctions, followed by a second implantation of ions of the same type as the first, at a higher dose than that of the first implantation in order to form the double junctions. The process is characterized in that between the first and second implantations, a conductive layer is epitaxied on said first junctions and on the gates, the second implantation being formed through the epitaxied layer in such a way that the double junctions are partly formed there.
    Type: Grant
    Filed: February 12, 1992
    Date of Patent: May 24, 1994
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Simon Deleonibus
  • Patent number: 5310689
    Abstract: A SIMOX structure having a reduced number of defects is formed by performing a two step anneal. In one embodiment, a conventional anneal is followed by an H.sub.2 /Si anneal. The conventional anneal first densifies the buried oxide layer in order to make the oxide less reactive with hydrogen. The H.sub.2 /Si anneal forms a quasi-equilibrium at the superficial semiconductor layer surface, thus there is no etching of the silicon surface and there is only a negligible amount of silicon deposition. The H.sub.2 reacts with the oxide precipitates and dissolves them. In a second embodiment the two step anneal comprises a low temperature H.sub.2 anneal followed by a conventional anneal. At low temperature, H.sub.2 can diffuse through silicon, but is much less reactive. Thus, etching of the superficial silicon and silicon dioxide buried layer is minimal. The conventional anneal is at a higher temperature, thus H.sub.2 can react with the oxygen precipitates to remove them.
    Type: Grant
    Filed: April 2, 1990
    Date of Patent: May 10, 1994
    Assignee: Motorola, Inc.
    Inventors: Mamoru Tomozane, H. Ming Liaw
  • Patent number: 5308791
    Abstract: An apparatus for processing the surface of an Si wafer includes a vacuum cleaning chamber in which said Si wafer is housed. He gas is supplied into the cleaning chamber and micro-wave and magnetic field are applied to the He gas to generate excited species which emit vacuum ultraviolet. The vacuum ultraviolet is radiated onto the wafer surface to enable its energy to cut bonds between Si atoms of said wafer and O atoms and forming a natural oxide film on the wafer surface. Ar gas is also supplied into the cleaning chamber to create ions of said Ar gas due to energy added from said excited species. Said ions are supplied onto the wafer surface to form floating potential above said wafer surface. Said ions collide against said wafer surface to eliminate O atoms from said wafer surface. A process chamber is connected to the cleaning chamber through a load lock chamber. Al film is formed on the wafer surface, from which the natural oxide film has been eliminated, in the process chamber.
    Type: Grant
    Filed: March 9, 1992
    Date of Patent: May 3, 1994
    Assignees: Tokyo Electron Limited, Yasuhiro Horiike
    Inventors: Yasuhiro Horiike, Kohei Kawamura
  • Patent number: 5306648
    Abstract: A photoelectric conversion device having a photoelectric conversion section and a transistor for transferring or amplification of the photoelectric conversion signal or an accumulating section of a photo carrier. The photoelectric conversion section and the transistor or the accumulating section have common semiconductor layer.
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: April 26, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masaki Fukaya, Soichiro Kawakami, Satoshi Itabashi, Katsunori Terada, Ihachiro Gofuku, Katsumi Nakagawa, Katsunori Hatanaka, Yoshinori Isobe, Toshihiro Saika, Tetsuya Kaneko, Nobuko Kitahara, Hideyuki Suzuki
  • Patent number: 5306660
    Abstract: Method and apparatus for vapor phase free methyl radical transport of indium dopant species for precise predetermined reproducible doping concentrations to control electrical properties for MOCVD grown materials.
    Type: Grant
    Filed: February 19, 1991
    Date of Patent: April 26, 1994
    Assignee: Rockwell International Corporation
    Inventors: Charles R. Younger, Shawn L. Johnston, Stuart J. C. Irvine, Edward R. Gertner, Kenneth L. Hess
  • Patent number: 5306663
    Abstract: A method of wiring a semiconductor device which allows a manufacturing step to be simplified without deteriorating an insulation characteristic of an aerial wiring. The semiconductor device wiring apparatus formed thereby includes a first beam column 1a disposed above a substrate 50 and a second beam column 1b disposed horizontally thereto. A wiring portion of the aerial wiring to be formed upwardly is formed by using the first beam column 1a and a wiring portion to be formed horizontally to wiring layer of the substrate 50 is formed by using the second beram column, which results in that no insulating film for the aerial wiring is required to simplify manufacturing steps.
    Type: Grant
    Filed: April 27, 1992
    Date of Patent: April 26, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroaki Morimoto
  • Patent number: 5298452
    Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon on a plurality of substrates in a hot wall, isothermal deposition system is described. The deposition temperatures are less than about 800.degree. C., and the operating pressures during deposition are such that non-equilibrium growth kinetics determine the deposition of the silicon films. An isothermal bath gas of silicon is produced allowing uniform deposition of epitaxial silicon films simultaneously on multiple substrates. This is a flow system in which means are provided for establishing an ultrahigh vacuum in the range of about 10.sup.-9 Torr prior to epitaxial deposition. The epitaxial silicon layers can be doped in-situ to provide very abruptly defined regions of either n- or p-type conductivity.
    Type: Grant
    Filed: February 21, 1992
    Date of Patent: March 29, 1994
    Assignee: International Business Machines Corporation
    Inventor: Bernard S. Meyerson
  • Patent number: 5296392
    Abstract: In a semiconductor substrate, a method of forming a shallow isolation trench having a doped sidewall is disclosed. A shallow trench having nearly vertical walls is formed in the semiconductor substrate. A doped silicon layer is selectively grown on a sidewall and a portion of the bottom of the trench. The dopant from the silicon layer is then driven into the substrate by a suitable method such as annealing. The trench is subsequently filled with a dielectric material.
    Type: Grant
    Filed: February 24, 1992
    Date of Patent: March 22, 1994
    Assignee: Digital Equipment Corporation
    Inventors: Gregory J. Grula, Walter C. Metz
  • Patent number: 5296385
    Abstract: Several process flows are proposed for achieving suitable wafer backside structures for integrated RTP-based device processing. The wafer backside conditions proposed here can be adapted for integrated fabrication process flows based on multiple integrated single-wafer and rapid thermal processing (RTP) cycles. These backside conditions ensure repeatable RTP uniformity and accurate pyrometry calibrations and measurements. The use of a highly doped layer near the wafer backside ensures negligible infrared transmission and repeatable RTP-based process uniformity, both for the high-temperature and the lower temperature RTP-based processes such as low-pressure chemical-vapor deposition of silicon. Two backside layers are used (oxide and nitride) to prevent dopant outdiffusion and backside oxide growth due to thermal oxidation. Moreover, the backside silicon nitride layer preserves uniform backside emissivity throughout the entire flow.
    Type: Grant
    Filed: March 3, 1992
    Date of Patent: March 22, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Mehrdad M. Moslehi, John Kuehne, Lino Velo
  • Patent number: 5296719
    Abstract: A quantum wire is formed at the top of triangular protrusion of silicon substrate. A quantum wire is isolated from the substrate by silicon oxide layers. A quantum wire is isolated from the substrate by impurity layers of a conduction type different from that of the substrate. An insulator film and a gate electrode are formed at the edge of triangular protrusion of a silicon substrate, and a quantum wire is induced by applying a voltage to the gate electrode. A quantum wire structure is fabricated by forming saw-tooth-like protrusions having (111) side planes by performing anisotropic crystalline etching and by oxidizing the silicon substrate with use of the oxide protection film to remain only around the top of the protrusions unoxidized. In another method, an oxide film is formed except around the top of the protrusions whereby a quantum wire is formed at the unoxidized region. In a different method, impurity layers are formed except around the top of the protrusions by ion implantation.
    Type: Grant
    Filed: July 20, 1992
    Date of Patent: March 22, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiko Hirai, Juro Yasui, Yasuaki Terui, Kiyoshi Morimoto, Atsuo Wada, Kenji Okada, Shin Hashimoto, Shinji Odanaka, Masaaki Niwa, Kaoru Inoue
  • Patent number: 5294560
    Abstract: A bidirectional nonlinear resistor for use as a nonlinear active element having a highly insulating organic film formed on a first conductor by polymerizing in an electrolytic solution containing a supporting electrolyte and a soluble organic compound, and a second conductor identical or not identical in kind with the first conductor formed on the organic film is provided. An active matrix substrate including a plurality of the bidirectional nonlinear resistor elements may be used to have a liquid crystal display panel. In a preferred embodiment, the electrolytic solution includes an alkali hydroxide as a supporting electrolyte so that dopant need not be removed after formation of the film. The electrolytic solution which is electrolytically polymerized to form the insulating organic film includes a monomer, preferably pyrrole, pyrrole derivatives, phenol or phenol derivatives, dissolved in an electrolytic solution.
    Type: Grant
    Filed: March 26, 1991
    Date of Patent: March 15, 1994
    Assignee: Seiko Epson Corporation
    Inventors: Yoshihiro Ono, Fumiaki Matsushima, Kuniyasu Matsui, Tetsuya Osaka
  • Patent number: 5294557
    Abstract: A method for ion-implanting a dopant species in semiconductors includes the steps of implanting a dopant species in a semiconductor material at a predetermined rate, the predetermined rate being based on a rate corresponding to a maximum in a characteristic graph of percent activation as a function of dopant species implantation rate; and annealing the dopant implanted semiconductor.
    Type: Grant
    Filed: August 26, 1991
    Date of Patent: March 15, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Frederick G. Moore, Harry B. Dietrich
  • Patent number: 5294570
    Abstract: A substantial reduction in the foreign particulate matter contamination on surfaces, such as the surfaces of semiconductor wafers, is achieved by treating the surfaces with a solution comprising a strong acid and a very small amount of a fluorine-containing compound. A preferred method employs a solution containing sulfuric acid, hydrogen peroxide and a very small amount of hydrofluoric acid, which is effective in reducing foreign particulate matter contamination, without significant etching, of the surface being treated.
    Type: Grant
    Filed: January 29, 1992
    Date of Patent: March 15, 1994
    Assignee: International Business Machines Corporation
    Inventors: Marshall J. Fleming, Jr., William A. Syverson, Eric J. White
  • Patent number: 5292373
    Abstract: An apparatus for washing a wafer, having a wafer-washing tank holding a washing liquid and receiving a wafer, a washing-liquid inlet provided in a first part of the sidewall of the tank, a washing-liquid outlet provided in a second part of the sidewall of the tank opposite to the first part of the sidewall, and a device holding the wafer in the tank so that the wafer is parallel to the level of the washing liquid when the wafer is immersed into or positioned in the washing liquid in the tank, and a device producing an essentially horizontal flow of the washing liquid in the tank. A process for washing a wafer, having the steps of producing a horizontal flow of the washing liquid in the tank, immersing a wafer cassette holding the wafer into the washing liquid in the tank so that the wafer is parallel to the level of the washing liquid in the tank, and subsequently positioning the cassette in the washing liquid in the tank so that the wafer is parallel to the level of the washing liquid in the tank.
    Type: Grant
    Filed: July 9, 1992
    Date of Patent: March 8, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naomi Arita, Yoshitaka Dansui
  • Patent number: 5290709
    Abstract: According to the present invention, in the ion implantation step in manufacturing a semiconductor device, a resist of a resist pattern formed on a portion of a semiconductor wafer is removed from the outer peripheral portion of the semiconductor wafer, and ion implantation is performed through the resist pattern.Since the resist is removed from the outer peripheral portion, a contact portion between a semiconductor wafer fixing portion of an ion implantation unit and the semiconductor wafer is conductive. Therefore, charges generated by the ion implantation escape from the wafer fixing portion, and the semiconductor wafer is not charged, thereby preventing electrostatic breakdown.
    Type: Grant
    Filed: April 9, 1992
    Date of Patent: March 1, 1994
    Assignee: NEC Corporation
    Inventor: Akira Sato
  • Patent number: 5288662
    Abstract: A process for thermal oxidation of silicon or cleaning of furnace tubes used in semiconductor manufacturing by exposing the silicon or tube to temperatures above 700.degree. C. while flowing a carrier gas containing oxygen and a chlorohydrocarbon having a general formula C.sub.x H.sub.x Cl.sub.x where x is 2, 3, or 4 over the silicon or tube. The chlorohydrocarbon is selected to readily and completely oxidize at temperature.
    Type: Grant
    Filed: June 15, 1992
    Date of Patent: February 22, 1994
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Andre Lagendijk, Arthur K. Hochberg, David A. Roberts
  • Patent number: 5286658
    Abstract: A semiconductor device is produced by a process for intrinsic gettering heat treatment of a silicon crystal in which the concentration of C--O complex defects destined to form seeds for oxygen precipitation in the silicon crystal is increased or an amount of oxygen precipitate in the silicon crystal is controlled, to thereby eliminate the dispersion of the amount from one crystal to another. In the heat treatment of the silicon crystal, the amount of oxygen precipitation can be controlled with a high accuracy.
    Type: Grant
    Filed: March 5, 1992
    Date of Patent: February 15, 1994
    Assignee: Fujitsu Limited
    Inventors: Yoshimi Shirakawa, Hiroshi Kaneta
  • Patent number: 5286657
    Abstract: A semiconductor wafer processing system utilizing a specially constructed wet processing chamber for a single wafer and a megasonic, or high frequency, energy dispensing system. The construction of the container causes megasonic energy to become intensified near the surface of the wafer, thereby providing more cleaning power, and resulting cleaning. The megasonic device may be mounted on a bottom wall dump valve. Also, the energy output may be used to rotate a wafer.
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: February 15, 1994
    Assignee: Verteq, Inc.
    Inventor: Mario E. Bran