Abstract: Rapid thermal annealing for heat-treating a semiconductor substrate is provided without damaging the substrate surface After the semiconductor substrate is placed in an annealing apparatus having an incoherent light source, an inert gas containing a very small amount of an oxygen gas is introduced into the annealing apparatus, while applying an incoherent light to the substrate surface from the incoherent light source. In this case, the oxygen concentration in the inert gas is defined by 10 to 1000 ppm.

Abstract: A method of manufacturing a semiconductor device having the steps of: forming a plurality of gate electrodes on a semiconductor substrate; forming an insulating film on every second gate electrode of the plurality of gate electrodes; coating resist on the whole surface of the semiconductor device to form a first resist film; patterning the first resist film and removing a predetermined area to form a second resist film, the end face of the second resist film being aligned with the surface of the gate electrode without the insulating film; implanting impurity ions, using the second resist film as a mask, at an acceleration voltage allowing to stop the implanted ions near to the surface of the semiconductor substrate under the gate electrode with the insulating film, of those gate electrodes not covered with the second resist film; removing the second resist film and coating resist on the whole surface of the semiconductor device to form a third resist film; patterning the third resist film and removing a prede

Abstract: Alkyl arsines are made by a reaction of gaseous arsine and the corresponding gaseous olefin in contact with at least one Bronsted acid catalyst. Products produced thereby are mono- and di-substituted arsines, e.g. alkyl and di-alkyl arsines, which contain substantially no metallic or oxygenating impurities.

Abstract: A silicon thin-film is formed on a silicon carbide (SiC) semiconductor body through the use of the thermal decomposition of monosilane (SiH.sub.4) gas. The thus formed silicon thin-film is oxidized by a thermal oxidation method which employs an oxygen gas so as to form a silicon oxide film of about 600 to 1200 .ANG. on the silicon carbide (SiC) semiconductor. The silicon oxide film shows a sharp boundary between the silicon carbide (SiC) semiconductor.An aluminum electrode is formed on the silicon oxide film, thereby providing a MOS structure on the silicon carbide (SiC) semiconductor.

Abstract: A sensor (210) for diagnosis and prognosis of semiconductor device fabrication processes measures specular, scattered, and total surface reflectances and transmittances of semiconductor wafers (124). The sensor (210) comprises a sensor arm (212) and an opto-electronic control box (214), for directing coherent electromagnetic or optical energy in the direction of semiconductor wafer (124). Opto-electronic control box (214) includes circuitry for measuring the amounts of laser powers coherently reflected from and transmitted through the semiconductor wafer (124) surface and the amounts of electromagnetic powers scatter reflected from and transmitted through the semiconductor wafer (124) surface. The present invention determines specular, scattered, and total reflectance and transmittance as well as surface roughness values for semiconductor wafer (124) based on measurements of coherent and scatter reflected and transmitted laser powers.

Abstract: An STM memory medium comprising a substrate whose surface is smooth or even, a first insulating layer formed at a predetermined depth in the substrate by implanting first ion atoms from the smooth surface of the substrate into it under a certain condition, and a second insulating layer formed adjacent to the first insulating layer and at another predetermined depth in the substrate by implanting second ion atoms from the smooth surface of the substrate into it under another certain condition.

Abstract: A dynamic holographic display has an array of reflective surfaces formed on cantilever structures substantially parallel to the surface of a substrate, such as a silicon wafer. A holographic image is formed by controlling electrical currents passed through the cantilever structures to position the reflective surfaces of the cells in the array so the topography forms a hologram, and reflected light interferes to form a holographic image. In a preferred embodiment, control is by computer and positions of reflective surfaces are determined by calculation from dimensional data available to the control computer.

Abstract: The electromigration characteristics of integrated circuit conductors are determined by passing a high current for a short period of time through an inventive test structure. This provides a rapid test in a more accurate manner than with the prior art SWEAT (Standard Wafer-level Electromigration Accelerated Test) structure. The test results have been found to be well correlated with long-term low current electromigration tests. A sensitive differential test may be implemented that determines the effects of topography features. The inventive test technique can be performed on every wafer lot, or even every wafer, so that adjustments to the wafer fabrication process can be rapidly implemented.

Abstract: A novel optical subassembly arrangement is proposed. The subassembly comprises a silicon-based submount including a plurality of openings for placement of the various optical components utilized to form the optical subassembly. In particular, a silicon wafer is processed (e.g., etched) using conventional techniques to simultaneously form a large number of individual submounts, each submount processed to include a number of openings. The silicon processing may be sufficiently controlled such that active alignment of the components is minimized. An important feature of the design, when associated with an isolated embodiment, is that the silicon submount is formed to include openings for both the laser and isolator optics such that the openings are disposed along a thermal transport path through the silicon substrate from an attached thermoelectric cooler (TEC). Therefore, the laser and isolator optics are maintained at the same operating temperature.

Abstract: A process for forming GaAs on a silicon substrate with very low levels of unintended silicon doping. First, a dielectric layer of silicon dioxide, silicon nitride, or both is grown or deposited on the substrate. Next, a window is opened in the dielectric layer exposing the silicon substrate in the regions in which the GaAs is to be formed. The GaAs layer is then formed on the substrate using conventional techniques with the gas phase transfer of silicon contamination from the edges and back of the silicon substrate to the GaAs region inhibited by the dielectric layer or layers.

Abstract: The present invention comprises a method of fabricating devices and circuits employing at least one heteroepitaxial layer under strain. The thickness of the heteroepitaxial layer is more than two times the calculated equilibrium critical thickness for an uncapped heteroepitaxial layer upon a crystalline substrate, based on previously known equilibrium theory for the uncapped layer. Subsequent to growth of the heteroepitaxial layer, the structure is processed at temperatures higher than the growth temperature of the heteroepitaxial layer.The strained heteroepitaxial layer (second layer) is epitaxially grown upon the surface of a first, underlaying crystalline layer, creating a heterojunction. Subsequently a third crystalline layer is deposited or grown upon the major exposed surface of the second, strained heteroepitaxial layer. The preferred manner of growth of the third crystalline layer is epitaxial growth.

Abstract: A method of fabricating a silicon film with improved thickness control and low defect density. The method comprises implanting a silicon wafer (19) with hydrogen ions to produce a layer of n-type silicon (18) having a precisely controlled thickness. Bonding the n-type silicon layer (18) to an oxidized surface (17) of a handle wafer (21) while using a temperature of 200 degrees Celsius. Etching the silicon wafer (19) to the boundary of the n-type layer (18). Annealing the silicon to drive out the hydrogen ions, leaving a silicon film (18) with a precisely controlled thickness and of the same type as the original silicon wafer (19).

Abstract: A method of manufacturing ferroelectric sensors having piezoelectric and pyroelectric properties are provided. These sensors include a semiconductor transistor having a gate and a surface layered with an integral film comprising a substantially poled ferroelectric polymer. The integral film is electrically connected to ground or a voltage source and to the gate of the semiconductor transistor. The preferred integral film is deposited on the semiconductor transistor using spin coating techniques. Extremely sensitive acoustic imaging sensors and the like can be produced in accordance with the invention which have high voltage sensitivity and better acoustic impedance match with body tissues and water.

Abstract: A method for thermal annealing of amorphous surface layers on a single-crystal semiconductor base element. The amorphous surface layer is obtained by implantation of germanium or silicon ions in a single-crystal silicon base element. Finally, the amorphous layer is doped by implantation of impurities and subjected to a three-step annealing process. During the first step of this process, the interface region between the amorphous layer and the single-crystal base element is smoothed at a temperature between 400.degree. and 460.degree. C., in the second step the amorphous layer recrystallizes at a temperature between 500.degree. and 600.degree. C., and in the third step the dopants are activated in an RTA process.

Abstract: A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.

Abstract: A wide band-gap semiconductor, such as a II-VI semiconductor having low bipolar resistivity and a method for producing such a semiconductor. To form this semiconductor, atomic hydrogen is used to neutralize compensating contaminants. Alternatively, the semiconductor dopant and hydrogen are introduced into the undoped semiconductor together, and later, the hydrogen is removed leaving an acceptably compensation free wide band-gap semiconductor.

Abstract: A semiconductor wafer (32) is patterned to have gettering areas (36-38) selectively positioned proximate devices (44-46) which require gettering. The areas (36-38) comprise germanium-doped silicon having a germanium concentration of approximately 1.5%-2.0%. The germanium creates a lattice mismatch between the substrate (32) and an epitaxial layer (34) which is sufficient to produce defects capable of gettering contaminants. The gettering areas (36-38) may be formed by selective deposition, selective etching, ion-implantation or selective diffusion techniques.

Abstract: Semiconductor wafers and other electronic parts which similarly require ultra-high purity manufacturing environments are treated with ultra-high purity liquid cleaning and etching agents prepared at the site of use from gaseous raw materials which have been purified to a level compatible with semiconductor manufacturing standards, combined when appropriate with ultra-pure water.

Abstract: A method and structure for forming a trench within a semiconductor layer (12) of material is provided. A first mask structure comprising a third insulating layer (20) and a fourth insulating layer (22) is formed adjacent a semiconductor layer (12). Sidewall spacers comprising a first and second portion (30) and (32) are formed along the sidewall (25) of layers (20) and (22) and extending outwardly the refrom. A second mask structure comprising a field insulating region (36) is formed adjacent first sidewall spacer portions (30) and along semiconductor layer (12). The foot portions (34) of first sidewall spacer portions (30) are removed thereby defining an exposed area (38) between the first mask structure and second mask structure. A trench (40) may then be formed between the two mask structures and filled with dielectrical material in order to isolate a semiconductor mesa (42) from semiconductor regions (44a) and 44b).

Abstract: A method of forming patterned films on a semiconductor substrate 10 includes the steps of depositing a hardened photo resist underlay 30 onto the substrate, then depositing a polyether sulfone release layer 32, then depositing a photo sensitive resist layer 34 and exposing an etching a metallization pattern 36, 38 to the substrate 10. The structure is then blanket deposited with a conductive layer 40 to thereby create a conductive contact stud 42. The film layer 40 and resist layer 34 are removed by dissolving the polyether sulfone layer 32 in an NMP solution and the photo resist underlayer 30 is then removed using a selective photo resist stripper composition.