Abstract: A semiconductor device has a semiconductor substrate, an insulated gate field-effect transistor section formed in the substrate and a peripheral section formed in the substrate and arranged to substantially surround the field-effect transistor section. A passivation layer of an organic material is provided over that part of the substrate in which the field-effect transistor section is not located. The device may be resin mold packaged for an enhanced humidity-resistance by making use of the fact tht the peripheral portion of the device is covered with organic resin.

Abstract: A method of manufacturing SIMOX heterostructures using a single implant sequence and an increasing range of ion beam energies is disclosed. The method produces SIMOX materials having thin, continuous buried oxide layers having sharp interfaces and which are substantially free of silicon islands.

Abstract: A semiconductor wafer cleaning apparatus provided with an ice making unit and a jet nozzle for ejecting fine ice particles against a wafer held within a cleaning vessel includes an exhaust chamber having an expanded portion and connected to the cleaning vessel. Curved guide plates extend from cleaning vessel into the exhaust chamber equidistant from each other into the expanded portion to guide the jet particles into the expanded portion. A flow regulator plate having a multitude of inverted frustum-shaped tapered holes regulates the jetted particles within the cleaning bath in accordance with the downward flow direction. Further, the upward flow from the exhaust chamber along the side walls is caught by stopper plates and exhausted via exhaust ports.

Abstract: A process for forming a Si-containing Al film of good quality according to the CVD method utilizing an alkyl aluminum hydride, a gas containing silicon and hydrogen, which is an excellent deposited film formation process also capable of selective deposition of Si-containing Al.

Abstract: The aim of the method is to prevent parasitic metallizations on the lateral walls of a raised pattern, which is used to self-align the electrode metallizations in a transistor. To this effect, a pair of semiconductor materials is introduced into the vertical pattern. These semiconductor materials react differently with respect to a pair of etching methods, so that a layer of one semiconductor material is etched to a greater extent than the other layer. The overhanging feature thus created interrupts the parasitic metallizations, if any, between the electrodes. The disclosed method can be applied to vertical structures.

Abstract: A DRAM cell of a stack structure having a cup-shaped polysilicon storage electrode for being applied to a 16 mega and 64 mega DRAM wherein a transfer transistor is firstly manufactured, a bit line is formed, an oxide film grid is formed between the cell and cell in the minimum design rule, and upon completing this, the polysilicon storage electrode is formed into a single or double cup shape, whereby the capacitor area is remarkably increased when compared with the conventional stacked structure DRAM cell so that the area efficiency is greatly increased and the process can be executed by such a mask number as the prior stacked structure mask layer number and the structure thereof is simple.

Abstract: An EPROM cell on a semiconductor substrate having a trench containing a source region in the bottom thereof, insulated floating gates on opposite sidewalls of the trench, and a control gate overlying the floating gates. Drain regions are provided beneath the top surface of the substrate, adjacent to the floating gates, which are electrically connected by a conductive stripe on the surface of the substrate that extends transverse to the trench axis.A method of fabricating an EPROM cell by forming a trench in a semiconductor substrate. An insulated floating gate of polycrystalline silicon is formed on the sidewalls of the trench. Doped regions are formed on the surface of the substrate and in the trench bottom. A control gate is formed over the floating gate. Electrical contact is established to the doped regions and the control gate.

Abstract: By providing a deposited film formation method in which aluminum or a metal composed mainly of aluminum of good quality is selectively deposited according to the CVD method utilizing an alkyl aluminum hydride and hydrogen, and then pure aluminum or a metal composed mainly of aluminum is non-selectively deposited, it becomes possible to form an electroconductive film of good quality within fine openings or on an insulating layer.

Abstract: A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor had various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.

Abstract: A process for forming an Al film of good quality according to the CVD method utilizing the reaction between alkyl aluminum hydride and hydrogen, which is an excellent deposited film formation process also capable of selective deposition of A1.

Abstract: A method of forming isolation trenches in CMOS integrated circuits is disclosed. The trench side walls are covered by a thin oxide layer, and the trenches are filled with a highly doped polysilicon. The doped polysilicon has a high work function which prevents oxide charges from inverting the trench side walls and thereby turns off the parasitic transistors at these side walls to reduce latchup.

Abstract: Channels extending partially through and vias extending completely through an insulating layer in an electrical interconnect such as a substrate or integrated circuit can be formed in a relatively few steps with low cost etching and patterning techniques. The channels and vias can then be filled with an electrical conductor in a relatively few steps. In one embodiment a non-erodible hard mask exposing the vias and channels is placed over a polyimide layer, an erodible soft mask exposing the vias but covering the channels is placed over the hard mask, and a plasma etch is applied. The via regions are etched until the soft mask completely erodes and then both the via and channel regions are etched to provide partially etched channels and fully etched vias. Thereafter a seed layer is deposited over the interconnect, and an electrically conductive layer is electrolytically deposited over the seed layer substantially filling the channels and vias.

Abstract: A method for the passivation of crystal defects in polycrystalline or amorphous silicon material using a temperature treatment step in a hydrogen-containing atmosphere the method results in favorable diode properties and favorable passivation properties in amorphous or, respectively, polycrystalline silicon material in a simple manner. Hydrogen-oxygen compounds are reduced at the surface of the silicon material, creating atomic hydrogen that diffuses into the silicon material.

Abstract: In a method for determining an end of cleaning of a semiconductor manufacturing apparatus according to the invention, when the interior of a semiconductor substrate process chamber of the semiconductor manufacturing apparatus is cleaned by dry etching using plasma discharge, a constant current or voltage is supplied from a high-frequency power source to discharge electrodes during plasma discharge, an impedance between the electrodes or a temperature in the process chamber is monitored, a time point at which the impedance or temperature is abruptly changed is detected, and this time point of detection is determined to be an end of cleaning.

Abstract: Disclosed is a method of making a semiconductor device that comprises MBE at substrate temperatures substantially lower than conventionally used temperatures. A significant aspect of the method is the ability to produce highly doped (e.g., 10.sup.19 cm.sup.-3) epitaxial single crystal Si layers. The deposition can be carried out such that substantially all (at least 90%) dopant atoms are electrically active at 20.degree. C. However, the method is not limited to Si MBE. Exemplarily, the method can be used to produce epitaxial single crystal GaAs having very short (e.g., <100ps) carrier lifetime. Such material can be useful for, e.g., high speed photodetectors. Incorporation into the method of a relatively low temperature rapid thermal anneal makes possible low temperature MBE growth of relatively thick semiconductor layers.

Abstract: A method for rinsing a textile wash load is provided for use in a vertical axis washing machine in which a plurality of initial spray rinses are used in which the released water is discharged directly to drain and a plurality of subsequent spray rinses are used in which the water is recirculated through the spinning clothes load for a predetermined length of time before being discharged to drain. Enhanced detergent and soil removal with less water usage is achieved with this method.

Abstract: According to the invention, a protective film which is separated from an integrated circuit part and partly buried in the semiconductor wafer is formed in the surface region of semiconductor wafer along a scribing line between adjacent integrated circuit parts. Upon cutting or dicing along the scribing lines, a portion of the protective film may remain along the edges thereof. Thus, the periphery of the semiconductor chips produced by dicing is protected by the protective film, and if an external force is applied to the periphery of the semiconductor chip in the dicing process or die-bonding process, the force is absorbed by the protective film and is hence lessened.

Abstract: The invention relates to a new method for cleaning chemical, metallic and particulate contaminants from solid surfaces. The new method comprises irradiating the surface with essentially ultraviolet laser radiation whose parameters are selected to avoid causing substantial chemical or physical change at the surface.

Abstract: An electrically programmable read only memory contains alternating metal bit lines and diffused bit lines. Each diffused bit line is broken into a plurality of segments. Each of the segments of the diffused bit line comprises a virtual source. A multiplicity of floating gate transistors are arranged in rows and columns. The floating gate transistors in each column are divided into M groups of N floating gate transistors each. The floating gate transistors in the n.sup.th and the (n+1).sup.th columns, where n is an odd integer given by 1.ltoreq.n.ltoreq.N and (N+1) is the maximum number of columns in the array are connected to the segments of one diffused bit line placed between the n.sup.th and the (n+1).sup.th columns. At least one first transfer transistor is arranged to connect one segment comprising a virtual source to a first metal bit line. The first metal bit line functions as the source for the N floating gate transistors in the (n+1).sup.th column connected to said one segment.

Abstract: A method of making a semiconductor integrated circuit provided with an isolating region constituted of an upper and lower isolating regions, and integrated circuit element regions is disclosed, wherein: the lower isolating region is diffused upward to a depth of a little more than half the thickness of an epitaxial layer to link with the upper isolating region prior to a doping of the upper isolating region; the doping of the lower isolating region and integrated circuit element regions, is implemented by means of ion implantation through a resist film which is capable of blocking ions implanted and in which specified doping windows have been formed in advance, and a SiO.sub.2 film is used as a reference mask in an ion implanting step, and the respective borders of the upper isolating region and the specified regions of the circuit elements is determined by self-alignment.