Abstract: A photoelectric conversion device has a non-single-crystal semiconductor laminate member formed on a substrate having a conductive surface, and a conductive layer formed on the non-single-crystal semiconductor laminate member. The non-single-crystal semiconductor laminate member has such a structure that a first non-single-crystal semiconductor layer having a P or N first conductivity type, an I-type second non-single-crystal semiconductor layer and a third non-single-crystal semiconductor layer having a second conductivity type opposite the first conductivity type are laminated in this order. The first (or third) non-single-crystal semiconductor layer is disposed on the side on which light is incident, and is P-type. The I-type non-single-crystal semiconductor layer has introduced thereinto a P-type impurity, such as boron which is distributed so that its concentration decreases towards the third (or first) non-single-crystal semiconductor layer in the thickwise direction of the I-type layer.

Abstract: A process for fabricating a stacked capacitor for use in monolithic integrated circuits using oxygen implantation. This invention provides a relatively simple process for manufacturing stacked capacitors having two series of interleaved plates. The process is unique, in that rather than requiring the use of a different material for each series of conductive plates, utilizes polycrystalline silicon for both series. The process proceeds with the deposition of alternating dielectric and polycrystalline silicon ("poly") layers, beginning and ending with a dielectric layer. Each poly layer is masked with photoresist, implanted with oxygen in unmasked regions, and then thermally annealed to convert all silicon in the unmasked regions into silicon dioxide. Each non-implanted poly region is horizontally offset from the non-implanted poly regions of the nearest superjacent and subjacent poly layers, which are, themselves, horizontally aligned.

Abstract: A susceptor for use in a vertical vapor growth apparatus includes a susceptor body (12) having an upper surface, a plurality of wafer receiving portions (17) formed in the upper surface of the susceptor body (12), and plates (16) fixed in the upper surface of the susceptor body (12) near the wafer setting portions (17). The plates (16) have an upper surface such that, when wafers (5) are mounted in the wafer setting portions (17), the upper surfaces of the plates (16) and the wafers (5) are positioned substantially in the same plane. The plates (16) are made of quartz glass or fused silica.

Abstract: A slotted metallic die attach pad is disclosed for attachment of a semiconductor die, such as a silicon die, to form a die assembly demonstrating significantly reduced die attach stress. A plurality of substantially parallel, unidirectional slots in the die attach pad permits deformation of the die attach pad at the slots to compensate for differences in the thermal expansion coefficients of the silicon die and the metallic die attach pad. Stress sensitive components of the die are aligned in a stress sensitive direction, and the die is bonded on the die attach pad so that the stress sensitive direction is generally orthongonal to the longitudinal axes of the slots. A method for relieving die stress in a die assembly is also disclosed.

Abstract: First, silicon wafers are formed by cutting silicon monocrystalline ingot into slices. Then back side and main surfaces of the wafers are subjected to lapping and etching processes. Next, the wafers are submerged into substantially pure water and ultrasonic waves are applied to the wafer surface via the water to clean at least one of the surfaces of each of the wafers and form gettering damage on the wafer surface. After this, the main surfaces of the wafers which have been subjected to the cleaning and damage-forming process and on which semiconductor elements are to be formed are polished into mirror finish.

Abstract: Process for neutralizing acceptor atoms in p-type InP.This process consists of subjecting to epitaxy a p-doped InP layer (4) and then a not intentionally doped Ga.sub.0.47 In.sub.0.53 As layer (6) on an InP semiinsulating substrate (2), followed by hydrogenating the InP layer exposing the assembly to a hydrogen plasma (8) with a power density below 0.07 W/cm.sup.2 at the most 250.degree. C.

Abstract: A process is described for fabricating a self-aligned lateral silicon-controlled rectifier circuit which includes the steps of forming an insulating layer 18 on a semiconductor substrate which includes an upper N-type region 12, 15 and a lower P-type region 10, and then forming an impurity mask 21 on the insulating layer 18. Portions of the insulating layer 18 adjacent the impurity mask 21 are then removed, and P conductivity type impurity 33 is introduced into the substrate 15 except where it is protected by the impurity mask 21. Finally, N-type impurity is introduced, also adjacent the impurity mask 21. When the structure is annealed, the impurity is diffused partially beneath the impurity mask to create a lateral SCR structure having a narrow PNP base width.

Abstract: A cleaning method and a gettering method for semiconductor wafers comprises blasting frozen particles at the surface of a semiconductor wafer. A processing apparatus for a semiconductor wafer comprises means for forming ultrafine frozen particles and means for blasting the frozen particles at the surface of a semiconductor wafer to perform either the gettering or the cleaning of the semiconductor wafer. In one form of the invention, the frozen particles are formed by spraying a mist of water into a chamber partially filled with liquid nitrogen, which freezes the mist to form ice particles. In another form of the invention, the frozen particles are formed by spraying a mist of water into a chamber containing cold nitrogen gas, which freezes the mist to form ice particles.

Abstract: A method of fabrication of a device having laterally isolated semiconductor regions. In a preferred embodiment, laterally isolated polysilicon features are created with vertical, nitride-sealed sidewalls. The nitride-sealed sidewalls formed using sidewall spacer technology eliminate oxide encroachment while further preventing the loss of dopant laterally during thermal processing. The final structure comprises polysilicon features flanked by either oxide isolation or additional polysilicon features and is planar without requiring a planarization etchback. The process is applicable to polysilicon electrodes over active areas as well as polysilicon resistors over isolation oxide.

Abstract: An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.

Abstract: A method for removal of scale from heat transfer equipment in which the scale contaminated surface is first contacted with a cleaning composition consisting essentially of an aqueous solution of hydroxyacetic acid and a polysaccharide gum and then contacted with a dilute aqueous solution of citric acid.

Abstract: A process for the fabrication of CMOS devices is disclosed in which a selectively doped silicon layer is selectively oxidized to provide a differential thickness in the silicon and in the overlaying silicon oxide. In accordance with one embodiment, a semiconductor substrate is provided having a layer of silicon overlaying a surface of that substrate. A first area of the layer of silicon is selectively doped with N-type impurities while a second area is left undoped. The silicon is thermally oxidized to form a thermal oxide having a greater thickness over the N-type doped area than over the undoped area. Correspondingly, the silicon under the thick thermal oxide has a lesser thickness than the silicon under the thin thermal oxide. The layer of silicon is patterned to form gate electrodes and interconnects, with some of the gate electrodes formed from the silicon having N-type dopant and some of the gate electrodes formed from the silicon which is not doped N-type.

Abstract: DMD projection light values for HDTV have various manufacturing requirements, including the high yield integration of the DMD superstructure on top of an underlying CMOS address circuit. The CMOS chip surface contains several processing artifacts that can lead to reduced yield for the DMD superstructure. A modified DMD architecture and process are disclosed that minimizes the yield losses caused by these CMOS artifacts while also reducing parasitic coupling of the high voltage reset pulses to the underlying CMOS address circuitry.

Abstract: In a method for determining an end of cleaning of a semiconductor manufacturing apparatus according to the invention, when the interior of a semiconductor substrate process chamber of the semiconductor manufacturing apparatus is cleaned by dry etching using plasma discharge, a constant current or voltage is supplied from a high-frequency power source to discharge electrodes during plasma discharge, an impedance between the electrodes or a temperature in the process chamber is monitored, a time point at which the impedance or temperature is abruptly changed is detected, and this time point of detection is determined to be an end of cleaning.

Abstract: A method for descaling the inside of a jacket of a glass-lined instrument by using a cleaning solution containing a detergent and an inhibitor is disclosed, wherein the amount of hydrogen permeated through the matrix of the instrument to the lining glass side is estimated by measuring a rate of hydrogen permeation through the jacket material or a test piece fitted to the circulation line of the cleaning solution and inserting the measured value into a previously established relationship between thickness of a steel plate and a rate of hydrogen permeation, and the concentrations of the detegent and the inhibitor in the cleaning solution, the descaling temperature or the descaling time is controlled so that the rate of hydrogen permeation through the matrix may not exceed 30 ml per m.sup.2 of the matrix during the descaling. A relatively large amount of scales can be rapidly and easily removed without causing breaking of the lining glass due to hydrogen permeation while minimizing corrosion of the matrix.

Abstract: In a method, especially for stripping enamel and removing coatings from objects, the advantages of a solvent treatment are to be retained, without having to put up with the disadvantages of contaminating the environment. This is accomplished essentially by using in a closed treating vessel a treating mixture with at least a preponderance of a solvent with a proportion of water in excess of that required for an azeotropic mixture and carrying out the treatment while boiling the treating mixture. After the treating mixture is removed from the vessel, any solvent components still present are distilled off azeotropically from the system with water and removed before the vessel is opened.

Abstract: A method is described for producing an integrated circuit structure, including EPROMS, having excellent resistance to penetration by moisture and ion contaminants and a substantial absence of voids in an underlying metal layer in the structure, and, in the case of EPROMS, maintaining sufficient UV light transmissity to permit erasure which comprises stress relieving the underlying metal layer from stresses induced by the compressive stress of a silicon nitride encapsulating layer to inhibit the formation of voids therein by implanting the metal layer with ions to change the grain structure adjacent the surface of the metal layer; forming an insulating intermediate layer between said the layer and the silicon nitride layer selected from the class consisting of an oxide of silicon and silicon oxynitride having a compressive/tensile stress which sufficiently compensates for the compressive stress of the silicon nitride layer; and controlling the compressive stress in the silicon nitride layer to provide resistan

Abstract: A motor is disclosed wherein electro-static repulsion and attraction between electrically charged electrodes provided on a stator and the charges on the surface of a pair of rotor electrodes are used to drive the rotor to rotate within the stator. In another embodiment the moving element is a rod or plate disposed for linear movement in an axial direction according to the charges developed in the stator electrode. The moving element electrode may have a lead by which it can be directly connected to an electric potential or it may be completely isolated from ground and from any electric potential.

Abstract: A reagent chemical is directed along a first pipe portion (20) that extends along one side of the array of wafers (14) and which contains a plurality of jets (33) for projecting the chemical toward the wafers. A plurality of second pipe portions (21) transmits an inert gas, with each pipe portion having a plurality of jets (34) for projecting the gas toward the floor of the tank.

Abstract: A method for washing a deposition film-forming device for forming deposition films comprises removing the reaction product attached on the interior of the reaction vessel during formation of the deposition film with ClF.sub.3 gas.