Patents Examined by Pamela E Perkins
  • Patent number: 9646832
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: May 9, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 9640566
    Abstract: A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: May 2, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji-Young Park, Yu-Gwang Jeong, Sang Gab Kim, Joon Geol Lee
  • Patent number: 9640421
    Abstract: Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 2, 2017
    Assignee: ARTILUX, INC.
    Inventors: Szu-Lin Cheng, Shu-Lu Chen
  • Patent number: 9633909
    Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 25, 2017
    Assignee: STMicroelectronics, Inc.
    Inventors: Walter Kleemeier, Qing Liu
  • Patent number: 9634213
    Abstract: Provided is a light emitting device with improved light extracting efficiency and further higher heat releasing performance. A light emitting device includes a planar lead frame having a first lead and a second lead, and includes a light emitting element mounted on the first lead, a resin frame surrounding a periphery of the light emitting element, a first sealing resin filled in the inner side of the resin frame and sealing the light emitting element, and a second sealing resin covering the resin frame and the first sealing resin. Lower end of inner surface of the resin frame is arranged only on the first lead, and at an outside of the resin frame, and the second resin member covers at least a part of the first lead and the second lead. Of the back-surface of the first lead, a region directly under the blight emitting element is exposed.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: April 25, 2017
    Assignee: NICHIA CORPORATION
    Inventor: Hiroaki Ukawa
  • Patent number: 9634086
    Abstract: A first doped region is formed in a single crystalline semiconductor substrate. Light ions are implanted through a process surface into the semiconductor substrate to generate crystal lattice vacancies between the first doped region and the process surface, wherein a main beam axis of an implant beam used for implanting the light ions deviates by at most 1.5 degree from a main crystal direction along which channeling of the light ions occurs. A second doped region with a conductivity type opposite to the first doped region is formed based on the crystal lattice vacancies and hydrogen atoms.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: April 25, 2017
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Johannes Georg Laven, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 9627548
    Abstract: A thin film transistor array panel that includes: a substrate; a gate electrode disposed on the substrate; a semiconductor layer disposed on the substrate; a gate insulating layer disposed between the gate electrode and the semiconductor layer; a source electrode disposed on the semiconductor layer and a drain electrode facing the source electrode; a metal oxide layer covering the source electrode and the drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the metal oxide layer, wherein the source electrode and the drain electrode include a first material and a second material which is added to the first material and metal included in the metal oxide layer is formed by diffusing the second material.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: April 18, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Ju Kang, Dong Hee Lee, Gwang Min Cha, Sang Won Shin, Sang Woo Sohn
  • Patent number: 9627208
    Abstract: According to an embodiment, a semiconductor switch includes a first insulating film on a semiconductor substrate, a first semiconductor layer on the first insulating film, a semiconductor switch circuit on the first semiconductor layer, and a wiring on the first insulating film. The first insulating film being between the wiring and the substrate. The wiring connects the semiconductor switch circuit and a terminal. A polycrystalline semiconductor layer is between the wiring and the first insulating film.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: April 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Ishimaru, Masami Nagaoka
  • Patent number: 9614088
    Abstract: A semiconductor structure includes a substrate including a first active region, a second active region and an isolation disposed between the first active region and the second active region; a plurality of gates disposed over the substrate and including a first gate extended over the first active region, the isolation and the second active region, and a second gate over the first active region and the second active region; and an inter-level dielectric (ILD) disposed over the substrate and surrounding the plurality of gates, wherein the second gate is configured not to conduct current flow and includes a first section disposed over the first active region and a second section disposed over the second active region, a portion of the ILD is disposed between the first section and the second section.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: April 4, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Shuo Ho, Tsung-Yu Chiang, Kuang-Hsin Chen
  • Patent number: 9611567
    Abstract: Provided is a method for controlling a donor concentration in a Ga2O3-based single crystal body. In addition, an ohmic contact having a low resistance is formed between a Ga2O3-based single crystal body and an electrode. A donor concentration in a Ga2O3-based single crystal body is controlled by a method which includes a step wherein Si, which serves as a donor impurity, is introduced into the Ga2O3-based single crystal body by an ion implantation method at an implantation concentration of 1×1020 cm?3 or less, so that a donor impurity implanted region is formed in the Ga2O3-based single crystal body, the donor impurity implanted region having a higher donor impurity concentration than the regions into which Si is not implanted, and a step wherein Si in the donor impurity implanted region is activated by annealing, so that a high donor concentration region is formed.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: April 4, 2017
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Patent number: 9607905
    Abstract: A method of measuring a breakdown voltage of a semiconductor element includes the steps below. A wafer provided with a plurality of semiconductor elements each having an electrode is prepared. The wafer is divided into a plurality of chips provided with at least one semiconductor element. After the step of division into the plurality of chips, a breakdown voltage of the semiconductor element is measured while a probe is in contact with the electrode of the semiconductor element in an insulating liquid.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: March 28, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Mitsuhiko Sakai, Susumu Yoshimoto
  • Patent number: 9608216
    Abstract: A flexible display device includes a flexible substrate including a display region and a peripheral region substantially surrounding the display region, the display region including a first display region and a second display region, a first display structure at the first display region of the flexible substrate, the first display structure including nanoparticles, and a second display structure at the second display region of the flexible substrate, the second display structure including silicon.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: March 28, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jun-Hyuk Cheon
  • Patent number: 9608094
    Abstract: A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: March 28, 2017
    Assignee: IMEC VZW
    Inventors: Anne S. Verhulst, Geoffrey Pourtois, Rita Rooyackers
  • Patent number: 9598278
    Abstract: The present disclosure is directed to a device that includes a substrate and a sensor formed on the substrate. The sensor includes a chamber formed from a plurality of integrated cavities, a membrane above the substrate, the membrane having a plurality of openings, each opening positioned above one of the cavities, and a plurality of diamond shaped anchors positioned between the membrane and the substrate, the anchors positioned between each of the cavities. A center of each opening is also a center of one of the cavities.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: March 21, 2017
    Assignee: STMICROELECTRONICS PTE LTD.
    Inventors: Olivier Le Neel, Tien Choy Loh
  • Patent number: 9599852
    Abstract: A method of manufacturing a liquid crystal optical device such as a lens, a beam steering device or an optical image stabilization device is described. The method includes edge bonding a thin substrate onto a carrier substrate to obtain a combined substrate; manipulating the combined substrate by the carrier substrate for wafer level fabricating at least one liquid crystal optical device on the central portion of the first thin substrate. Each liquid crystal optical device includes liquid crystal cell walls. To form the at least one liquid crystal optical device a second thin substrate is provided and bonded to the combined substrate. The cell walls support and interconnect the thin first substrate to the second thin substrate. The at least one liquid crystal optical device is singulated by dicing the combined substrate within the peripheral bonding zone.
    Type: Grant
    Filed: August 5, 2014
    Date of Patent: March 21, 2017
    Assignee: Lensvector, Inc.
    Inventor: Tigran Galstian
  • Patent number: 9590085
    Abstract: A method for fabricating a semiconductor device comprises forming a fin in a layer of III-V compound semiconductor material on a silicon-on-insulator substrate; forming a semiconductor extension on the fin, the semiconductor extension comprising a III-V compound semiconductor material that is different from a material forming the fin in the III-V compound semiconductor layer; forming a dummy gate structure and a spacer across and perpendicular to the fin; forming a source/drain layer on a top surface of the substrate adjacent to the dummy gate structure; planarizing the source/drain layer; removing the dummy gate structure to expose a portion of the semiconductor extension on the fin; removing the exposed portion of the semiconductor extension; etching the semiconductor extension to undercut the spacer; and forming a replacement gate structure in place of the removed dummy gate structure and removed exposed portion of the semiconductor extension.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: March 7, 2017
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 9589842
    Abstract: A method of fabricating a semiconductor package is disclosed. The method includes disposing semiconductor chips on a support substrate, forming a protection layer covering top surfaces of the semiconductor chips, forming a molding layer covering the support substrate and the protection layer, and etching the molding layer to expose the protection layer.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: March 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inho Choi, Donghan Kim, Jae Choon Kim, Jikho Song, Mitsuo Umemoto
  • Patent number: 9589957
    Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: March 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ju-Youn Kim
  • Patent number: 9590201
    Abstract: An organic light emitting diode display has uniform light emission efficiency over the entire pixel area. The organic light emitting diode display comprises: a substrate having a red pixel area, a green pixel area, and a blue pixel area arrayed in a matrix; an anode electrode in the red, green, and blue pixel areas; a hole injection layer including an organic material with an extinction coefficient less than about 0.13 and on the anode electrode covering a whole surface of the substrate; an emission layer on the hole injection layer; an electron injection layer on a whole surface of the emission layer; and a cathode electrode on a whole surface of the electron injection layer.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 7, 2017
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jeonghaeng Heo, Taesun Yoo, Taeshick Kim, Seung Kim
  • Patent number: 9589996
    Abstract: A method for manufacturing a display device includes providing a first substrate, forming at least one first capacitor on the first substrate, providing a second substrate having a gate drive element formed thereon, and bonding the first substrate in alignment with the second substrate.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: March 7, 2017
    Assignees: SHANGHAI AVIC OPTO ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Huijun Jin, Dongliang Dun, Xin Xu, Wantong Shao, Chen Chen