Abstract: A method of manufacturing a light-emitting diode comprises the steps of providing a substrate comprising an upper surface and a bottom surface opposite to the upper surface; providing a semiconductor stack layer on the upper surface, wherein the semiconductor stack layer comprises a first type semiconductor layer having a first surface, a light-emitting layer on the first type semiconductor layer for emitting light, and a second type semiconductor layer on the light-emitting layer; treating the first surface to form a second surface, wherein the second surface is flatter than the first surface; and providing a laser beam through the second surface to cut the substrate.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier layer is disposed over the substrate and between the substrate and the electrically conductive layer. A dielectric layer is disposed over the moisture barrier layer. The dielectric layer has an elastic modulus that is lower than an elastic modulus of the moisture barrier layer.

Abstract: Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region.

Abstract: Sensor packages and manners of formation are described. In an embodiment, a sensor package includes a supporting die characterized by a recess area and a support anchor protruding above the recess area. A sensor die is bonded to the support anchor such that an air gap exists between the sensor die and the recess area. The sensor die includes a sensor positioned directly above the air gap.

Abstract: The present invention provides a method for preparing a silicon dioxide substrate-based graphene transparent conductive film, which comprises: preparing a silicon dioxide substrate on a graphene transparent conductive film, thereby obtaining a silicon dioxide substrate-based graphene transparent conductive film. In the method for preparing a silicon dioxide substrate-based graphene transparent conductive film according to the embodiments of the present invention, the silicon dioxide substrate is prepared on the graphene transparent conductive film, and a graphene transferring step that is difficult to implement in the prior art can be avoided, thus the silicon dioxide substrate-based graphene transparent conductive film can be prepared conveniently, and the cost may be reduced at the same time.

Abstract: Transmission lines with a first dielectric material separating signal traces and a second dielectric material separating the signal traces from a ground plane. In embodiments, mutual capacitance is tuned relative to self-capacitance to reverse polarity of far end crosstalk between a victim and aggressor channel relative to that induced by other interconnect portions along the length of the channels, such as inductively coupled portions. In embodiments, a transmission line for a single-ended channel includes a material of a higher dielectric constant within the same routing plane as a microstrip or stripline conductor, and a material of a lower dielectric constant between the conductor and the ground plane(s). In embodiments, a transmission line for a differential pair includes a material of a lower dielectric constant within the same routing plane as a microstrip or stripline conductors, and a material of a higher dielectric constant between the conductors and the ground plane(s).

Abstract: An integrated circuit package may include an integrated circuit die with lower and upper surfaces. The integrated circuit die is mounted on a package substrate. An underfill material is deposited between the integrated circuit die and the package substrate. A molding compound may be injected to surround the integrated circuit die while leaving the upper surface of the integrated circuit die exposed. The integrated circuit package further includes a metal layer that contacts the exposed upper surface of the integrated circuit die. The metal layer may also cover the molding compound. If desired, an additional metal layer may be formed on the layer of metal as a heat spreader. Such a configuration may also be applicable for wire bond packages, in which the metal layers are formed on an overmold that is disposed over a wire-bonded integrated circuit die on a package substrate.

Abstract: Methods of fabricating solar cell emitter regions using silicon nano-particles and the resulting solar cells are described. In an example, a method of fabricating an emitter region of a solar cell includes forming a region of doped silicon nano-particles above a dielectric layer disposed above a surface of a substrate of the solar cell. A layer of silicon is formed on the region of doped silicon nano-particles. At least a portion of the layer of silicon is mixed with at least a portion of the region of doped silicon nano-particles to form a doped polycrystalline silicon layer disposed on the dielectric layer.

Abstract: A semiconductor device includes a first semiconductor chip comprising a first metallic structure and a second semiconductor chip comprising a second metallic structure. The second semiconductor chip is bonded with the first semiconductor chip by a first conductive plug. A second conductive plug extends from the first metallic structure and into a substrate of the first semiconductor chip. The first conductive plug connects the first metallic structure and the second metallic structure, wherein a conductive liner is along a sidewall of the first conductive plug or the second conductive plug.

Abstract: A light-emitting device includes a support body having a quadrangle planar shape, a wiring pattern on the support body, a light-emitting element on the wiring pattern, a recognition target portion on a corner portion of the support body, the recognition target portion including a conductive material, an insulation layer reflecting light emitted from the light-emitting element and covering a periphery of the recognition target portion, and a light-transmissive member including a lens portion covering the light-emitting element and a flange portion on a periphery of the lens portion and covering a portion of the recognition target portion that is covered with the insulation layer. The portion of the recognition target portion covered by the flange portion is arranged in a non-point symmetry around a center of the support body, and a difference in reflectivity between the support body and the insulation layer is larger than between the support body and the recognition target portion.

Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

Abstract: The present invention discloses a polarizing filter and a display device. The polarizing filter comprises a polarization layer and a conductive layer provided on one side of the polarization layer. In the present invention, the conductive layer is provided on the polarization layer, thus, when the electrostatic charge are present on the color film substrate having the polarizing filter, the electrostatic charge may be shielded by the conductive layer, and will not adversely affect the liquid crystal molecule between the color film substrate and a array substrate celled to the color film substrate even if the charge are present on a surface of the color film substrate, such that the display quality of the display panel having the color film substrate and the array substrate is improved.

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract: A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of kinds of circuits and transistors whose electrical characteristics are different between the circuits is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes an oxide semiconductor, a conductor, a first insulator, a second insulator, and a third insulator. The conductor has a region where the conductor and the oxide semiconductor overlap with each other. The first insulator is positioned between the conductor and the oxide semiconductor. The second insulator is positioned between the conductor and the first insulator. The third insulator is positioned between the conductor and the second insulator. The second insulator has a negatively charged region.

Abstract: A method of processing a laminated wafer in which a first wafer is laminated on a second wafer, the method including: a laminated wafer forming step of forming the laminated wafer by laminating the first wafer on the second wafer; a modified layer forming step of forming a modified layer within the first wafer by positioning a focusing point of a laser beam within the first wafer and moving the first wafer in a horizontal direction relative to the focusing point while applying the laser beam, the modified layer forming step being performed before or after the laminated wafer forming step is performed; and a separating step of separating part of the first wafer from the laminated wafer with the modified layer as a boundary, the separating step being performed after the laminated wafer forming step and the modified layer forming step are performed.

Abstract: Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

Abstract: In an optical device wafer processing method, a light emitting layer on the front side of a wafer is removed by applying a pulsed laser beam to the wafer along division lines from the back side of a substrate with the focal point of the beam set near the light emitting layer, thereby partially removing the light emitting layer along the division lines. A shield tunnel is formed by applying the beam to the wafer along the division lines from the back of the substrate with the focal point of the beam set near the front of the substrate. This forms a plurality of shield tunnels arranged along each division line, each shield tunnel extending from the front side of the substrate to the back side thereof. Each shield tunnel has a fine hole and an amorphous region formed around the fine hole for shielding the fine hole.

Abstract: A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one embodiment, the material layers can be electrically conductive layers, and a contact via structure can contact the vertically coincident sidewalls. In another embodiment, a sacrificial spacer can be formed on the vertically coincident sidewalls, and the material layers and the sacrificial spacer can be replaced with a conductive material. A contact via structure can be formed on a set of layers electrically shorted by a vertical conductive material portion that is formed in a volume of the spacer. The contact via structure can provide electrical contact to multiple electrically conductive layers.

Abstract: Provided is a method of manufacturing an organic light-emitting device including a graphene layer. The method of manufacturing an organic light-emitting device according to the present invention may include providing a graphene donor unit including a patterned graphene layer, providing a device unit, and attaching the graphene layer of the graphene donor unit to an organic part. The device unit may include a substrate, a lower electrode, and the organic part which are sequentially stacked, and the organic part may include a dopant. The graphene donor unit may include the graphene layer, a release layer, and an elastic stamp layer which are sequentially stacked.