Patents Examined by Pamela E Perkins
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Patent number: 8736004Abstract: Reading margin is improved in a MTJ designed for MRAM applications by employing a pinned layer with an AP2/Ru/AP1 configuration wherein the AP1 layer is a CoFeB/CoFe composite and by forming a MgO tunnel barrier adjacent to the CoFe AP1 layer by a sequence that involves depositing and oxidizing a first Mg layer with a radical oxidation (ROX) process, depositing and oxidizing a second Mg layer with a ROX method, and depositing a third Mg layer on the oxidized second Mg layer. The third Mg layer becomes oxidized during a subsequent anneal. MTJ performance may be further improved by selecting a composite free layer having a Fe/NiFeHf or CoFe/Fe/NiFeHf configuration where the NiFeHf layer adjoins a capping layer in a bottom spin valve configuration. As a result, read margin is optimized simultaneously with improved MR ratio, a reduction in bit line switching current, and a lower number of shorted bits.Type: GrantFiled: July 15, 2013Date of Patent: May 27, 2014Assignee: Headway Technologies, Inc.Inventors: Wei Cao, Witold Kula, Chyu-Jiuh Torng
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Patent number: 8735290Abstract: A reactive evaporation method for forming a group III-V amorphous material attached to a substrate includes subjecting the substrate to an ambient pressure of no greater than 0.01 Pa, and introducing active group-V matter to the surface of the substrate at a working pressure of between 0.05 Pa and 2.5 Pa, and group III metal vapor, until an amorphous group III-V material layer is formed on the surface.Type: GrantFiled: November 19, 2008Date of Patent: May 27, 2014Assignee: Mosaic Crystal Ltd.Inventor: Moshe Einav
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Patent number: 8728913Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions that are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.Type: GrantFiled: July 2, 2013Date of Patent: May 20, 2014Assignee: SoitecInventors: Sébastien Kerdiles, Walter Schwarzenbach, Aziz Alami-Idrissi
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Patent number: 8728872Abstract: A method includes preparing a bonding surface of a heat dissipating member, applying flux to the bonding surface of the heat dissipating member, and removing excess flux from the bonding surface so that minimal flux is provided. The method also includes preparing a die surface of an electronic device package, applying flux to the die surface, and removing excess flux from the die surface so that minimal flux is provided. The method further includes positioning a preform solder component on the die surface, positioning the heat dissipating member over the die surface and the preform solder component such that the flux layer of the bonding surface is in contact with the preform solder component, and reflowing the solder component using a reflow oven. A heat spreader is also described for use in the process.Type: GrantFiled: August 18, 2011Date of Patent: May 20, 2014Assignee: DY 4 Systems, Inc.Inventors: Ivan Straznicky, Peter Robert Lawrence Kaiser, Steven Drennan, Marc-Jason Renaud, Georges Francis Marquis
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Patent number: 8722542Abstract: A method for patterning a layer at a bottom of a high aspect ratio feature of a substrate is described. The method includes providing the substrate having a first layer with a feature pattern overlying a second layer. The feature pattern is characterized with an initial critical dimension (CD), an initial corner profile, and an aspect ratio of 5:1 or greater. The method further includes etching through at least a portion of the second layer at the bottom of the feature pattern to extend the feature pattern at least partially into the second layer while retaining a final CD within a threshold of the initial CD and a final corner profile within a threshold of the initial corner profile using a gas cluster ion beam (GCIB) etching process.Type: GrantFiled: March 15, 2013Date of Patent: May 13, 2014Assignee: TEL Epion Inc.Inventors: Christopher K. Olsen, Luis Fernandez
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Patent number: 8716139Abstract: A method of patterning a semiconductor device including dividing a layout into more than one pattern. The method further includes depositing a film stack on a semiconductor substrate, depositing a hard mask on the film stack, and depositing a first photoresist on the hard mask. The method further includes patterning the first photoresist using a first pattern of the more than one pattern. The method further includes etching the hard mask to transfer a design of the first pattern of the more than one pattern to the hard mask. The method further includes depositing a second photoresist over the etched hard mask and patterning the second photoresist using a second pattern of the more than one pattern. The method further includes etching portions of the film stack exposed by a combination of the etched hard mask and the second photoresist.Type: GrantFiled: March 1, 2012Date of Patent: May 6, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: George Liu, Kuei Shun Chen, Meng Wei Chen
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Patent number: 8710516Abstract: A manufacturing method of a touch panel structure includes the following steps. A first conductive layer is formed on a mounting surface of a substrate, and the first conductive layer has multiple first electrodes. A first electrical-insulation layer is formed on the mounting surface of the substrate, and the first electrical-insulation layer covers each of the first electrodes of the first conductive layer. A second conductive layer is formed on the first electrical-insulation layer; the second conductive layer has multiple second electrodes, and each of the second electrodes crisscrosses each of the first electrodes. A second electrical-insulation layer is formed on the first electrical-insulation layer, and the second electrical-insulation layer covers each of the second electrodes of the second conductive layer.Type: GrantFiled: December 2, 2011Date of Patent: April 29, 2014Assignee: Fortrend Taiwan Scientific Corp.Inventor: Chih-Shun Chang
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Patent number: 8703515Abstract: Methods for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current-guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a substrate) may be provided. For some embodiments, both a current-guiding structure and second current path may be provided.Type: GrantFiled: August 26, 2013Date of Patent: April 22, 2014Assignee: SemiLEDS Optoelectronics Co., Ltd.Inventors: Wen-Huang Liu, Chen-Fu Chu, Jiunn-Yi Chu, Chao-Chen Cheng, Hao-Chun Cheng, Feng-Hsu Fan, Yuan-Hsiao Chang
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Patent number: 8698243Abstract: Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions.Type: GrantFiled: July 29, 2013Date of Patent: April 15, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper
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Patent number: 8692290Abstract: Device structures and design structures for a silicon controlled rectifier, as well as methods for fabricating a silicon controlled rectifier. The device structure includes first and second layers of different materials disposed on a top surface of a device region containing first and second p-n junctions of the silicon controlled rectifier. The first layer is laterally positioned on the top surface in vertical alignment with the first p-n junction. The second layer is laterally positioned on the top surface of the device region in vertical alignment with the second p-n junction. The material comprising the second layer has a higher electrical resistivity than the material comprising the first layer.Type: GrantFiled: September 7, 2011Date of Patent: April 8, 2014Assignee: International Business Machines CorporationInventors: Kiran V. Chatty, Robert J. Gauthier, Jr., Junjun Li, Alain Loiseau
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Patent number: 8685818Abstract: Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants.Type: GrantFiled: June 25, 2010Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Huiling Shang, Ying Li, Henry K. Utomo
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Patent number: 8679945Abstract: An integrated circuit is formed by coating a top surface of a wafer that has been processed through all integrated circuit chip manufacturing steps prior to backgrind with photoresist, applying backgrind tape over a top surface of the photoresist, backgrinding a back surface of the wafer to a specified thickness, removing the backgrind tape from the top surface of the photoresist, and removing the photoresist. The surface of the integrated circuit and any devices that may be bonded to the surface of the integrated circuit are protected by the photoresist layer during removal of the backgrind tape.Type: GrantFiled: March 5, 2012Date of Patent: March 25, 2014Assignee: Texas Instruments IncorporatedInventors: Gregory A. Moore, Tyonda Hill
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Patent number: 8673761Abstract: A reflow method for solder includes heating the solder to a first temperature that is above a liquidus temperature of the solder; cooling the solder to a second temperature that is below a solidification temperature of the solder; reheating the solder to a third temperature that is above a solidus temperature of the solder and below the liquidus temperature of the solder; cooling the solder to a fourth temperature that is below the solidification temperature of the solder.Type: GrantFiled: February 19, 2011Date of Patent: March 18, 2014Assignee: International Business Machines CorporationInventors: Pascal Blais, Clement Fortin
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Patent number: 8674454Abstract: A lateral bipolar junction transistor includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; and a collector region surrounding the base region; wherein the portion of the base region under the gate does not under go a threshold voltage implant process.Type: GrantFiled: February 20, 2009Date of Patent: March 18, 2014Assignee: Mediatek Inc.Inventors: Ching-Chung Ko, Tung-Hsing Lee
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Patent number: 8658493Abstract: An aluminum oxide film covering a ferroelectric capacitor is formed. Next, an opening (51t) where a portion of a top electrode is exposed and an opening (51b) where a portion of a bottom electrode is exposed are formed in the aluminum oxide film. Thereafter, films (23 to 26) are formed and a resist pattern (92) is formed. Then, etching of the films (23 to 26) is performed with using the resist pattern (92) as a mask thereby forming contact holes (27t) and (27b). At this time, since the openings (51t) and (51b) are formed in the aluminum oxide film, the aluminum oxide film is not required to be processed. Consequently, the contact holes (27t) and (27b) can be formed easily.Type: GrantFiled: August 11, 2009Date of Patent: February 25, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Kouichi Nagai
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Patent number: 8659040Abstract: One aspect of the present invention provides a semiconductor light-emitting device improved in luminance, and also provides a process for production thereof. The process comprises a procedure of forming a relief structure on the light-extraction surface of the device by use of a self-assembled film. In that procedure, the light-extraction surface is partly covered with a protective film so as to protect an area for an electrode to be formed therein. The electrode is then finally formed there after the procedure. The process thus reduces the area incapable, due to thickness of the electrode, of being provided with the relief structure. Between the electrode and the light-extraction surface, a contact layer is formed so as to establish ohmic contact between them.Type: GrantFiled: April 5, 2012Date of Patent: February 25, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Akira Fujimoto, Ryota Kitagawa, Koji Asakawa, Hidefumi Yasuda, Yasuhiko Akaike, Takeyuki Suzuki
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Patent number: 8652884Abstract: The present invention proposes a semiconductor device structure and a method for manufacturing the same, and relates to the semiconductor manufacturing industry. The method comprises: providing a semiconductor substrate; forming gate electrode lines on the semiconductor substrate; forming sidewall spacers on both sides of the gate electrode lines; forming source/drain regions on the semiconductor substrates at both sides of the gate electrode lines; forming contact holes on the gate electrode lines or on the source/drain regions; and cutting off the gate electrode lines to form electrically isolated gate electrodes after formation of the sidewall spacers but before completion of FEOL process for a semiconductor device structure. The embodiments of the present invention are applicable for manufacturing integrated circuits.Type: GrantFiled: February 27, 2011Date of Patent: February 18, 2014Assignee: The Institute of Microelectronics, Chinese Academy of SciencesInventors: Huicai Zhong, Qingqing Liang
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Patent number: 8647983Abstract: A method for bonding a first copper element onto a second copper element including forming a crystalline copper layer enriched in oxygen on each of surfaces of each of the first and second elements through which the elements will be in contact, the total thickness of both layers being less than 6 nm, which includes: a) polishing the surfaces so as to obtain a roughness of less than 1 nm RMS, and hydrophilic surfaces, b) cleaning the surfaces to suppress presence of particles due to the polishing and the major portion of corrosion inhibitors, and c) putting both crystalline copper layer enriched in oxygen in contact with each other.Type: GrantFiled: July 1, 2010Date of Patent: February 11, 2014Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMicroelectronics (Crolles 2) SASInventors: Lea Di Cioccio, Pierric Gueguen, Maurice Rivoire
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Patent number: 8647896Abstract: Provided is a process for producing a substrate for a liquid ejection head, including forming a liquid supply port in a silicon substrate, the process including the steps of (a) forming an etch stop layer at a portion of a front surface of the silicon substrate at which portion the liquid supply port is to be formed; (b) performing dry etching using a Bosch process from a rear surface side of the silicon substrate up to the etch stop layer with use of an etching mask formed on a rear surface of the silicon substrate to thereby form the liquid supply port; and (c) simultaneously removing the etch stop layer and a deposition film formed inside the liquid supply port.Type: GrantFiled: March 5, 2012Date of Patent: February 11, 2014Assignee: Canon Kabushiki KaishaInventor: Toshiyasu Sakai
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Patent number: 8642378Abstract: A method for forming a photovoltaic device includes patterning a dielectric layer on a substrate to form a patterned dielectric having local spacings between shapes and remote spacings between groups of shapes, and depositing a doped epitaxial layer over the patterned dielectric such that selective crystalline growth occurs in portions of the epitaxial layer in contact with the substrate and noncrystalline growth occurs in portions of the epitaxial layer in contact with the patterned dielectric. First metal contacts are formed over the local spacings of the patterned dielectric, and second metal contacts are formed over the remote spacings. Exposed portions of the noncrystalline growth are etched using the first and second metal contacts as an etch mask to form alternating interdigitated emitter and back contact stacks.Type: GrantFiled: December 18, 2012Date of Patent: February 4, 2014Assignee: International Business Machines CorporationInventors: Keith E. Fogel, Bahman Hekmatshoartabari, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
