Abstract: It is intended to provide a method of producing a semiconductor device, comprising the steps of: providing a substrate on one side of which at least one semiconductor pillar stands; forming a first dielectric film to at least partially cover a surface of the at least one semiconductor pillar; forming a conductive film on the first dielectric film; removing by etching a portion of the conductive film located on a top surface and along an upper portion of a side surface of the semiconductor pillar; forming a protective film on at least a part of the top surface and the upper portion of the side surface of the semiconductor pillar; etching back the protective film to form a protective film-based sidewall on respective top surfaces of the conductive film and the first dielectric film each located along the side surface of the semiconductor pillar; forming a resist pattern for forming a gate line in such a manner that at least a portion of the resist pattern is formed on the top surface of the semiconductor pillar

Abstract: A semiconductor device includes a first field effect transistor (FET) located on a substrate; and a second FET located on the substrate, the second FET comprising a first buried oxide (BOX) region located underneath a channel region of the second FET, wherein the first BOX region of the second FET is configured to cause the second FET to have a higher radiation sensitivity that the first FET.

Abstract: One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined contour is formed in one of a semiconductor membrane and a substrate wafer. The semiconductor membrane is bonded to the substrate wafer and the predetermined contour is straightened to induce a predetermined strain in the semiconductor membrane. In various embodiments, a substrate wafer is flexed into a flexed position, a portion of the substrate wafer is bonded to a semiconductor layer when the substrate wafer is in the flexed position, and the substrate wafer is relaxed to induce a predetermined strain in the semiconductor layer. Other aspects and embodiments are provided herein.

Abstract: A method of fabricating semiconductor light emitting device forms a laminated film by laminating an n-type nitride semiconductor layer, an active layer and a p-type nitride semiconductor layer in order on a uneven main surface of a first substrate, forms a plurality of first electrodes, on an upper surface of the p-type nitride semiconductor layer, forms a first metal layer to cover surfaces of the plurality of first electrodes and the p-type nitride semiconductor layer, forms a second metal layer on an upper surface of the second substrate, joins the first and second metal layers by facing the first and second substrates, cuts the first substrate or forming a groove on the first substrate along a border of the light emitting element from a surface side opposite to the first metal layer on the first substrate, and irradiates a laser toward areas of the light emitting devices from a surface side opposite to the first metal layer on the first substrate to peel off the first substrate.

Abstract: A simple and economical method for manufacturing very thin capped MEMS components. In the method, a large number of MEMS units are produced on a component wafer. A capping wafer is then mounted on the component wafer, so that each MEMS unit is provided with a capping structure. Finally, the MEMS units capped in this way are separated to form MEMS components. A diaphragm layer is formed in a surface of the capping wafer by using a surface micromechanical method to produce at least one cavern underneath the diaphragm layer, support points being formed that connect the diaphragm layer to the substrate underneath the cavern. The capping wafer structured in this way is mounted on the component wafer in flip chip technology, so that the MEMS units of the component wafer are capped by the diaphragm layer. The support points are then cut through in order to remove the substrate.

Abstract: A method of fabricating a semiconductor package. In one embodiment the method includes forming a mold cavity about a portion of a first major surface of a leadframe, including about a mold lock opening extending through the leadframe between the first major surface and a second major surface. A spacer is inserted to fill at least a portion of the mold lock opening. The mold cavity is filled with an encapsulating material including filling a portion of the mold lock opening not occupied by the spacer.

Abstract: The method may include providing a first substrate, the first substrate including a sacrificial layer, an active layer having an image sensor circuit portion and an interconnection layer electrically connected to the image sensor circuit portion sequentially stacked; performing an edge-trimming process with respect to the first substrate to form an interconnection layer pattern, an active layer pattern and a sacrificial layer pattern; adhering the first substrate to a second substrate; removing the sacrificial layer pattern to expose the active layer pattern; and forming a transillumination layer to provide light to an image sensor portion on the active layer pattern.

Abstract: A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer.

Abstract: A method is disclosed for singulating die from a semiconductor substrate (e.g. a semiconductor-on-insulator substrate or a bulk silicon substrate) containing an oxide layer (e.g. silicon dioxide or a silicate glass) and one or more semiconductor layers (e.g. monocrystalline or polycrystalline silicon) located above the oxide layer. The method etches trenches through the substrate and through each semiconductor layer about the die being singulated, with the trenches being offset from each other around at least a part of the die so that the oxide layer between the trenches holds the substrate and die together. The trenches can be anisotropically etched using a Deep Reactive Ion Etching (DRIE) process. After the trenches are etched, the oxide layer between the trenches can be etched away with an HF etchant to singulate the die. A release fixture can be located near one side of the substrate to receive the singulated die.

Abstract: While an adhesive layer is provided over the rear surface of a semiconductor chip in die bonding, a lamination processing (main pressure bonding) is necessary for securing the adhesive state of the adhesive layer after the die bonding process (temporary pressure bonding). In this case, typically the hardening of the adhesive is developed by applying heat while pressing down the rear surface of the chip from above with a pressurization member. It has become clear that various problems exist in the lamination processing of the laminate chips by such a mechanical pressurization method as the chip becomes thinner. That is, the problems include chip damage at a part in an overhang state, a chip position shift caused by bending and non-uniform pressurization, and the like.

Abstract: In a semiconductor substrate on which are formed an N-type MOS transistor and a P-type MOS transistor, the gate electrode of the N-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the gate electrode of the P-type MOS transistor comprises a tungsten film, which makes contact with a gate insulation film, and the concentration of carbon contained in the former tungsten film is less than the concentration of carbon contained in the latter tungsten film.

Abstract: A method for sealing an organic light emitting diode (OLED) device is disclosed wherein the OLED device comprises a color filter. A color filter is deposited on a first glass plate or substrate and a glass-based frit is then deposited in a loop around the color filter, The deposited fit loop is then heated by electromagnetic energy to evaporate organic constituents and to sinter the fit in a pre-sintering step. An OLED device may then be assembled by positioning a second glass plate comprising an organic light emitting material deposited thereon in overlying registration with the first glass plate, with the color filer and the organic light emitting material positioned between the plates. The fit is then heated with a laser to form a hermetic seal between the first and second glass plates.

Abstract: A solid-state imaging apparatus and a manufacturing method of a solid-state imaging apparatus are provided. Metal wirings 102 and 103 are formed in an effective pixel region A and out-of effective pixel region B of a semiconductor substrate 100, and an etch stop layer 118 is formed over the metal wirings 102 and 103. Moreover, an insulating film 119 is formed on the etch stop layer 118, and another metal wiring 104 is formed on the insulating film 119 in the out-of effective pixel region B. Next, the insulating film 119 in the effective pixel region A is removed by using the etch stop layer 118, and interlayer lenses 105 are formed in the step in the effective pixel region A where the insulating film 119 is removed.

Abstract: Crisscrossing spacers formed by pitch multiplication are used to form isolated features, such as contacts vias. A first plurality of mandrels are formed on a first level and a first plurality of spacers are formed around each of the mandrels. A second plurality of mandrels is formed on a second level above the first level. The second plurality of mandrels is formed so that they cross the first plurality of mandrels, when viewed in a top down view. A second plurality of spacers is formed around each of the second plurality of mandrels. The first and the second mandrels are selectively removed to leave a pattern of voids defined by the crisscrossing first and second pluralities of spacers. These spacers can be used as a mask to transfer the pattern of voids to a substrate. The voids can be filled with conductive material to form conductive contacts.

Abstract: Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.

Abstract: A fill-placement method, according to which symmetrical fill patterns are used to insert fill tiles into one or more interconnect levels corresponding to symmetrical circuitry. The fill-placement method can be used, for example, in the fabrication of an integrated circuit having at least two complementary portions for which relatively tight circuit-matching requirements need to be met.

Abstract: A surface component film (2) is etched using a resist (3) as a mask, and the surface component film (2) is patterned according to the shape of an aperture (3a). This results in a step portion (4) having the same shape as the aperture (3a), with the sidewall (4a) of the step portion (4) exposed through the aperture (3a). The aperture (3a) is spin-coated with a shrink agent, reacted at a first temperature, and developed to shrink the aperture (3a). To control the shrinkage with high accuracy, in the first round of reaction, the aperture is shrunk by, for example, about half of the desired shrinkage. The aperture (3a) is further spin-coated with a shrink agent, reacted at a second temperature, and developed to shrink the aperture (3a). In this embodiment, the second-round shrink process will result in the desired aperture length. The second temperature is adjusted based on the shrinkage in the first round.

Abstract: In a preferred method of formation embodiment, a metal foil or film is obtained or formed with micro-holes. The foil is anodized to form metal oxide. One or more self-patterned metal electrodes are automatically formed and buried in the metal oxide created by the anodization process. The electrodes form in a closed circumference around each microcavity in a plane(s) transverse to the microcavity axis, and can be electrically isolated or connected. Preferred embodiments provide inexpensive microplasma device electrode structures and a fabrication method for realizing microplasma arrays that are lightweight and scalable to large areas. Electrodes buried in metal oxide and complex patterns of electrodes can also be formed without reference to microplasma devices—that is, for general electrical circuitry.

Abstract: Provided is a bifacial photovoltaic arrangement comprising a bifacial cell which included a semiconductor layer having a first surface and a second surface, a first passivation layer formed on the first surface of the semiconductor layer and a second passivation layer formed on the second surface of the semiconductor layer, and a plurality of metallizations formed on the first and second passivation layers and selectively connected to the semiconductor layer. At least some of the metallizations on the bifacial photovoltaic arrangement comprising an elongated metal structure having a relatively small width and a relatively large height extending upward from the first and second passivation layers.

Abstract: In a first aspect, a method of forming a memory cell is provided, the method including: (1) forming a pillar above a substrate, the pillar comprising a steering element and a metal hardmask layer; (2) selectively removing the metal hardmask layer to create a void; and (3) forming a carbon-based switching material within the void. Numerous other aspects are provided.