Abstract: A chemical vapor deposition method for forming an aluminum-silicon nitride layer upon a substrate uses an aluminum precursor, a silicon precursor and a nitrogen precursor under chemical vapor deposition conditions to deposit the aluminum-silicon nitride layer upon the substrate. The aluminum-silicon nitride layer has an index of refraction interposed between silicon nitride and aluminum nitride. The aluminum-silicon nitride layer also has a bandgap from about 4.5 to about 6 eV and a permittivity from about 6×10^-11 to about 8×10^-11 F/m. The aluminum-silicon nitride layer may be further thermally annealed to reduce a hydrogen content of the aluminum-silicon nitride layer.

Abstract: A method of manufacturing an array substrate for an FFS mode LCD device includes forming a gate line, a gate electrode and a pixel electrode on a substrate; forming a gate insulating layer; forming a data line, source and drain electrodes, and a semiconductor layer on the gate insulating layer, the drain electrode overlapping the pixel electrode; forming a passivation layer on the data line, the source and drain electrodes; forming a contact hole exposing the drain electrode and the pixel electrode by patterning the passivation layer and the gate insulating layer; and forming a common electrode and a connection pattern on the passivation layer, wherein the common electrode includes bar-shaped openings and a hole corresponding to the contact hole, and the connection pattern is disposed in the hole, is spaced apart from the common electrode and contacts the drain electrode and the pixel.

Abstract: Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.

Abstract: A new method of electrophoretic nanotube deposition is proposed wherein individual nanotubes are placed on metal electrodes which have their length significantly exceeding their width, while the nanotube length is chosen to be close to that of the metal electrode. Due to electrostatic attraction of individual nanotube to the elongated electrode, every nanotube approaching the electrode is deposited along the electrode, since such an orientation is energetically favorable. This method offers opportunity to produce oriented arrays of individual nanotubes, which opens up a new technique for fabrication and mass production of nanotube-based devices and circuits. Several such devices are considered. These are MESFET- and MOSFET-like transistors and CMOS-like voltage inverter.

Abstract: Methods of fabricating solar cell emitter regions using silicon nano-particles and the resulting solar cells are described. In an example, a method of fabricating an emitter region of a solar cell includes forming a region of doped silicon nano-particles above a dielectric layer disposed above a surface of a substrate of the solar cell. A layer of silicon is formed on the region of doped silicon nano-particles. At least a portion of the layer of silicon is mixed with at least a portion of the region of doped silicon nano-particles to form a doped polycrystalline silicon layer disposed on the dielectric layer.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes forming first layer on first and second regions in substrate, first layer having first width in first region and having larger dimension than first width in second region, forming first sidewall on first layer, forming second layer covering first sidewall in the second region and forming third layer having second width smaller than first width on the side face of first sidewall having second width after removing first layer, forming second and third sidewalls having second width so that second and third sidewalls is adjacent to first sidewall across third layer by second width in first region and across second and third layers by second interval larger than second width in the second region.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming first and second cores on a processed material, forming a covering material having a stacked layer includes first and second layers, the covering material covering an upper surface and a side surface of the first and second cores, removing the second layer covering the first core, forming a first sidewall mask having the first layer on the side surface of the first core and a second sidewall mask having the first and second layers on the side surface of the second core by etching the covering material, removing the first and second cores, and forming first and second patterns having different width in parallel by etching the processed material in condition of using the first and second sidewall masks.

Abstract: A method of forming a polyimide film on a surface of a substrate by dehydration condensation of a first monomer including a bifunctional acid anhydride and a second monomer including a bifunctional amine is disclosed. The method includes loading the substrate into a processing chamber, heating the substrate at a temperature at which a polyimide film is formed, and performing a cycle a predetermined number of times. The cycle comprises supplying a first processing gas containing the first monomer to the substrate, supplying a second processing gas containing the second monomer to the substrate. The method further includes supplying a replacement gas in the processing chamber between supplying the first processing gas and supplying the second processing gas thereby replacing atmosphere in the processing chamber by the replacement gas, and evacuating the first and/or the second processing gas out of the processing chamber.

Abstract: A manufacturing method of a light emitting device is provided. A first electrode is formed on a substrate. The first electrode includes a patterned conductive layer, and the patterned conductive layer includes an alloy containing a first metal and a second metal. An annealing process is performed on the first electrode, so as to form a passivation layer at least on a side surface of the first electrode. The passivation layer includes a compound of the second metal. A light emitting layer is formed on the first electrode. A second electrode is formed on the light emitting layer.

Abstract: A solid-state imaging apparatus and a manufacturing method of a solid-state imaging apparatus are provided. Metal wirings 102 and 103 are formed in an effective pixel region A and out-of effective pixel region B of a semiconductor substrate 100, and an etch stop layer 118 is formed over the metal wirings 102 and 103. Moreover, an insulating film 119 is formed on the etch stop layer 118, and another metal wiring 104 is formed on the insulating film 119 in the out-of effective pixel region B. Next, the insulating film 119 in the effective pixel region A is removed by using the etch stop layer 118, and interlayer lenses 105 are formed in the step in the effective pixel region A where the insulating film 119 is removed.

Abstract: Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure involves forming a first layer of a first dielectric material overlying a doped region formed in a semiconductor substrate, forming a first conductive contact electrically connected to the doped region within the first layer, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and a gate structure overlying the semiconductor substrate, and forming a second conductive contact electrically connected to the gate structure within the second layer.

Abstract: According to one embodiment, a method of fabricating a semiconductor memory device includes patterning a first memory cell layer and a first interconnect layer to form a first structure of a linear pattern in a first region and a second structure in a second region, forming a second interconnect layer and a second memory cell layer, and patterning the second memory cell layer and the second interconnect layer to form, in the first region, a third structure having a linear pattern and having a folded pattern immediately on the second structure. The method further includes removing the second memory cell layer and the second interconnect layer in the folded pattern, and the first memory cell layer of the second structure positioned under the folded pattern.

Abstract: A method includes patterning a plurality of magnetic tunnel junction (MTJ) layers to form an MTJ cell, and forming a dielectric cap layer over a top surface and on a sidewall of the MTJ cell. The step of patterning and the step of forming the dielectric cap layer are in-situ formed in a same vacuum environment. A plasma treatment is performed on the dielectric cap layer to transform the dielectric cap layer into a treated dielectric cap layer, whereby the treated dielectric cap layer improves protection from H2O or O2, and thus degradation.

Abstract: A wafer processing method of dividing a wafer along streets. The wafer processing method includes a protective tape attaching step of attaching a protective tape to the front side of the wafer, a modified layer forming step of holding the wafer through the protective tape on a chuck table of a laser processing apparatus under suction and next applying a laser beam having a transmission wavelength to the wafer from the back side of the wafer along the streets, thereby forming a modified layer inside the wafer along each street, and a wafer dividing step of canceling suction holding of the wafer by the chuck table and next applying an air pressure to the wafer now placed on the holding surface in the condition where horizontal movement of the wafer is limited, thereby dividing the wafer along each street where the modified layer is formed, thus obtaining individual devices.

Abstract: An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a low-k dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the low-k dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the low-k dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer.

Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

Abstract: A polyimide film is effectively formed on a complicated surface. The polyimide film is formed by reacting, on the surface, diamine monomer and tetracarboxylic acid dianhydride monomer both of which are dissolved within carbon dioxide in a supercritical states, together with a polyamic acid resulting from a reaction between the diamine monomer and the tetracarboxylic acid dianhydride reached to the surface.

Abstract: A semiconductor device includes a metal substrate including a metal base plate, an insulating sheet located on the metal base plate, and a wiring pattern located on the insulating sheet, and a semiconductor element located on the metal substrate. The semiconductor element is sealed with a molding resin. The molding resin extends to side surfaces of the metal substrate. On the side surfaces of the metal substrate, the insulating sheet and the wiring pattern are not exposed from the molding resin, whereas the metal base plate includes a projecting portion exposed from the molding resin.

Abstract: Provided are a mask for an application of paste and a method of manufacturing a semiconductor light emitting device by using the same. The method includes preparing a light emitting structure including first and second conductive semiconductor layers and an active layer disposed therebetween, which has at least one electrode formed on a surface of the light emitting structure; disposing a mask having an open part exposing a portion of the surface of the light emitting structure therethrough and a recess part corresponding the electrode in a region thereof on a surface of the light emitting structure; and applying wavelength conversion material-containing paste to the surface of the light emitting structure through the open part.

Abstract: According to one embodiment, in a method of a nitride semiconductor light emitting device, a nitride semiconductor laminated body is formed on a first substrate having a first size. A first adhesion layer with a second size smaller than the first size is formed on the nitride semiconductor laminated body. A second adhesion layer is formed on a second substrate. The first and the second substrates are bonded while the first and second adhesion layers being overlapped each other. The first substrate is removed so as to generate a recess having a third size equal to or larger than the second size. The first substrate is etched until exposing the nitride semiconductor laminated body while injecting a chemical solution into the recess. The exposed nitride semiconductor laminated body is etched using the chemical solution so as to form a concave-convex portion in the exposed nitride semiconductor laminated body.