Abstract: The invention relates to a method (3) of fabricating a mold (39, 39?) including the following steps: (a) depositing (9) an electrically conductive layer on the top (20) and bottom (22) of a wafer (21) made of silicon-based material; (b) securing (13) the wafer to a substrate (23) using an adhesive layer; (c) removing (15) one part (26) of the conductive layer from the top of the wafer (21); and (d) etching (17) the wafer as far as the bottom conductive layer (22) thereof in the shape (26) of the one part removed from the top conductive layer (22) to form at least one cavity (25) in the mold. The invention concerns the field of micromechanical parts, particularly, for timepiece movements.

Abstract: A method for fabricating a vertical transistor comprises steps: forming a plurality of first trenches in a substrate; sequentially epitaxially growing a first polarity layer and a channel layer inside the first trenches, and forming a first retard layer on the channel layer; etching the first retard layer and the channel layer along the direction vertical to the first trenches to form a plurality of pillars; respectively forming a gate on a first sidewall and a second sidewall of each pillar; removing the first retard layer on the pillar; and epitaxially growing a second polarity layer on the pillar. The present invention is characterized by using an epitaxial method to form the first polarity layer, the channel layer and the second polarity layer and has the advantage of uniform ion concentration distribution. Therefore, the present invention can fabricate a high-quality vertical transistor.

Abstract: A method includes performing a laser grooving to remove a dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer. The trench is in a scribe line between two neighboring chips in the wafer. A polymer is filled into the trench and then cured. After the step of curing the polymer, a die saw is performed to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench.

Abstract: A method of forming an amorphous carbon layer on an insulating layer includes the step of forming an amorphous carbon layer using a plasma reaction process. The amorphous carbon layer is formed in an atmosphere containing a plasma excitation gas, a CxHy series gas, a silicon-containing gas, and an oxygen-containing gas.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of pillars by etching a semiconductor substrate, forming a gate dielectric layer on sidewalls of the pillars and on surfaces of the semiconductor substrate between the pillars, forming an implant damage in a portion of the gate dielectric layer between two pillars by implanting ions into the portion of the gate dielectric layer, forming vertical gates to cover the sidewalls of the pillars, and removing the implant damage.

Abstract: In a method of manufacturing a semiconductor device, a barrier metal film and an aluminum metal film are formed on an insulating film on a semiconductor substrate. Two aluminum electrodes are formed in parallel with each other by patterning the barrier metal film and the aluminum metal film. The aluminum metal film in a region of part of each of the two aluminum electrodes are selectively removed to form two single-layer barrier metal electrodes separated from each other. A resistor is formed between the two single-layer barrier metal electrodes so as to electrically connect the two single-layer barrier metal electrodes to each other.

Abstract: According to an embodiment of the invention, a magnetic tunnel junction (MTJ) element includes a reference ferromagnetic layer, a storage ferromagnetic layer, and an insulating layer. The storage ferromagnetic layer includes a CoFeB sub-layer coupled to a CoFe sub-layer and/or a NiFe sub-layer through a non-magnetic sub-layer. The insulating layer is disposed between the reference and storage ferromagnetic layers.

Abstract: It is an object to form a conductive region in an insulating film without forming contact holes in the insulating film. A method is provided, in which an insulating film is formed over a first electrode over a substrate, a first region having many defects is formed at a first depth in the insulating film by adding first ions into the insulating film at a first accelerating voltage; a second region having many defects is formed at a second depth which is different from the first depth in the insulating film by adding second ions into the insulating film at a second accelerating voltage, a conductive material containing a metal element is formed over the first and second regions; and a conductive region which electrically connects the first electrode and the conductive material is formed in the insulating film by diffusing the metal element into the first and second regions.

Abstract: Improved MOSFET devices are obtained by incorporating strain inducing source-drain regions whose closest facing “nose” portions underlying the gate are located at different depths from the device surface. In a preferred embodiment, the spaced-apart source-drain regions may laterally overlap. This close proximity increases the favorable impact of the strain inducing source-drain regions on the carrier mobility in an induced channel region between the source and drain. The source-drain regions are formed by epitaxially refilling asymmetric cavities etched from both sides of the gate. Cavity asymmetry is obtained by forming an initial cavity proximate only one sidewall of the gate and then etching the final spaced-apart source-drain cavities proximate both sidewalls of the gate along predetermined crystallographic directions.

Abstract: A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers.

Abstract: A method for forming an oxide film on a carbon film includes the steps of forming a carbon film on an object to be processed; forming an object-to-be-oxidized layer on the carbon film; and forming an oxide film on the object-to-be-oxidized layer while oxidizing the object-to-be-oxidized layer.

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

Abstract: A method includes arranging a bonding layer of a predetermined thickness on at least one of a first functional region bonded on a release layer, which is capable of falling into a releasable condition when subjected to a process, on a first substrate, and a region, to which the first functional region is to be transferred, on a second substrate; bonding the first functional region to the second substrate through the bonding layer; and separating the first substrate from the first functional region at the release layer.

Abstract: A method for fabricating a shaped thin-film photovoltaic device. The method includes providing a shaped substrate member including a surface region and forming a first electrode layer overlying the surface region. Additionally, the method includes forming an absorber comprising copper species, indium species, and selenide species overlying the first electrode layer. The method further includes scribing through the absorber using a mechanical tip to form a first pattern. Furthermore, the method includes forming a window layer comprising cadmium sulfide species overlying the absorber including the first pattern. Moreover, the method includes scribing through the window layer and the absorber using the mechanical tip to form a second pattern. The second pattern is separated a distance from the first pattern.

Abstract: A method of processing copper backside metal layer for semiconductor chips is disclosed. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by either electroless plating or sputtering. Then, the copper backside metal layer is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the copper backside metal layer through backside via holes, but also prevents metal peeling from semiconductor's substrate after subsequent fabrication processes, which is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes. The use of Pd as seed layer is particularly useful for the copper backside metal layer, because the Pd layer also acts as a diffusion barrier to prevent Cu atoms entering the semiconductor wafer.

Abstract: Reading margin is improved in a MTJ designed for MRAM applications by employing a pinned layer with an AP2/Ru/AP1 configuration wherein the AP1 layer is a CoFeB/CoFe composite and by forming a MgO tunnel barrier adjacent to the CoFe AP1 layer by a sequence that involves depositing and oxidizing a first Mg layer with a radical oxidation (ROX) process, depositing and oxidizing a second Mg layer with a ROX method, and depositing a third Mg layer on the oxidized second Mg layer. The third Mg layer becomes oxidized during a subsequent anneal. MTJ performance may be further improved by selecting a composite free layer having a Fe/NiFeHf or CoFe/Fe/NiFeHf configuration where the NiFeHf layer adjoins a capping layer in a bottom spin valve configuration. As a result, read margin is optimized simultaneously with improved MR ratio, a reduction in bit line switching current, and a lower number of shorted bits.

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.

Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.

Abstract: In a manufacturing method of a flash memory structure with a stress area, a better stress effect can be achieved by controlling the manufacturing process of a tunneling oxide layer formed in a gate structure and contacted with a silicon substrate, so that an L-shaped spacer (or a first stress area) and a contact etch stop layer (or a second stress area) of each L-shaped spacer are formed between two gate structures and aligned towards each other to enhance the carrier mobility of the gate structure, so as to achieve the effects of improving a read current, obtaining the required read current by using a lower read voltage, reducing the possibility of having a stress-induced leakage current, and enhancing the data preservation of the flash memory.

Abstract: The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions which are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs.