Patents Examined by Paresh Patel
  • Patent number: 12379399
    Abstract: A probe card device is provided, including a thin film substrate, a first circuit board, and a plurality of probes. The thin film substrate has opposite first and second surface. The first circuit board is disposed over the second surface of the thin film substrate to electrically connect the thin film substrate. The probes are disposed over the first surface of the thin film substrate and are not deformable.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: August 5, 2025
    Assignee: PRINCO CORP.
    Inventor: Pei-liang Chiu
  • Patent number: 12379413
    Abstract: A semiconductor test system has a test fixture with a plurality of test sites. Each test site has a DUT placement area and an electrical test circuit dedicated for a DUT to perform voltage and current testing. The electrical test circuit has a voltage measuring block and a current measuring block. The voltage measuring block has an analog-to-digital converter for converting an analog voltage measurement to a digital voltage measurement. The current measuring block has a resistor conducting a current to be measured, an amplifier with a first input and a second input coupled across the resistor, and an analog-to-digital converter with an input coupled to an output of the amplifier and an output for providing a digital current measurement. A test control system controls the test fixture. The electrical test circuit can be an integrated circuit or a discrete circuit.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: August 5, 2025
    Assignee: JCET STATS ChipPAC Korea Limited
    Inventors: YongJu Lee, SeongHyun Kang, JiWon Seong
  • Patent number: 12369245
    Abstract: Provided is a printed circuit board for degradation detection, the printed circuit board having an insulator substrate and a wiring pattern for degradation detection, the wiring pattern being formed on an outer surface of the insulator substrate, and the printed circuit board for degradation detection being attached to a main printed circuit board for which degradation is to be detected. The wiring pattern is formed on, of the outer surfaces of the insulator substrate, a back surface positioned on the main printed circuit board side. The insulator substrate has a penetrating part (through hole, notch part) penetrating from the back surface to a front surface positioned on the side opposite from the back surface.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: July 22, 2025
    Assignee: FANUC CORPORATION
    Inventors: Takeshi Sawada, Fuyuki Ueno
  • Patent number: 12360159
    Abstract: Various embodiments are described that relate to failure determination for an integrated circuit. An integrated circuit can be tested to determine if the integrated circuit is functioning properly. The integrated circuit can be subjected to a specific radiation such that the integrated circuit produces a response. This response can be compared against an expected response to determine if the response matches the expected response. If the response does not match the expected response, then the integrated circuit fails the test. If the response matches the expected response, then the integrated circuit passes the test.
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: July 15, 2025
    Assignee: The Government of the United States, as represented by the Secretary of the Army
    Inventors: Greg Rupper, John Suarez, Sergey Rudin, Meredith Reed, Michael Shur
  • Patent number: 12360155
    Abstract: An optical probe includes a core part and a clad part arranged along an outer circumference of the core part, and has an incident surface having a radius of curvature R through which an optical signal enters. The radius of curvature R and a central half angle ? at an incident point of the optical signal on the incident surface fulfil the following formulae using a radiation angle ? of the optical signal, an effective incident radius Se of the optical signal transmitted in the core part without penetrating into the clad part on the incident surface, a refractive index n(r) of the core part at the incident point, and a refracting angle ? at the incident point: R=Se/sin(?) ?=±sin?1{[K22/(K12+K22)]1/2} where K1=n(r)×cos(?)?cos(?/2) and K2=n(r)×sin(?)?sin(?/2).
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: July 15, 2025
    Assignee: Kabushiki Kaisha Nihon Micronics
    Inventors: Michitaka Okuta, Yuki Saito, Jukiya Fukushi
  • Patent number: 12355274
    Abstract: A device includes a first electronic component and a case, wherein the case includes a first charging compartment configured to accommodate and charge the first electronic component. The device further includes a first magnet included in the first electronic component and a 3D magnetic field sensor included in the case. The device further includes a detection unit configured to detect a position of the first electronic component relative to the first charging compartment based on a magnetic field sensed by the 3D magnetic field sensor.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: July 8, 2025
    Assignee: Infineon Technologies AG
    Inventors: Lifeng Guan, Wai Keung Frankie Chan
  • Patent number: 12352780
    Abstract: An integrated circuit (IC) device test socket has an integrally formed IC picking mechanism for removing an IC device from the test socket after testing. The test socket has a base member and a cover member. The base member includes a recess that is configured to receive an IC device for testing. The cover member is configured to removably engage the base member to secure the IC device between the cover member and the base member. The cover member includes an IC picking mechanism configured to use suction to retain the IC device to the cover member.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: July 8, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Yalaj Goyal, Shailesh R. Nayak, Joe Paul Moolanmoozha
  • Patent number: 12346287
    Abstract: A method for automatically detecting a sensor coupled to an electronic computer, including a second step, consisting of passing to a third step when the electronic computer is activated, the third step, consisting of comparing a voltage generated by the sensor coupled to the terminals of the electronic computer with a reference voltage, in the event that the result of the comparison is positive, then passing to a fourth step, and in the event that the result of the comparison is negative, passing to a fifth step, the fourth step, consisting of selecting an impedance matched to the coupling of the voltage-source sensor to the terminals of the electronic computer.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: July 1, 2025
    Assignee: Vitesco Technologies GmbH
    Inventors: Jacques Rocher, Yannick Leroy
  • Patent number: 12320882
    Abstract: A method is provided for determining source match of a test system including an RF source, a vector network analyzer (VNA) and a test port. The method includes connecting a first calibration standard to the test port; generating an RF signal using the RF source, and applying the RF signal to the first calibration standard; measuring a first incident signal of the RF signal at a first receiver of the test system, and measuring a first reflected signal at a second receiver of the test system; connecting a second calibration standard to the test port; measuring a second incident signal of the RF signal at the first receiver of the test system, and measuring a second reflected signal at the second receiver of the test system; and determining the source match of the test system using the first incident and reflected signals and the second incident and reflected signals.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: June 3, 2025
    Assignee: KEYSIGHT TECHNOLOGIES, INC
    Inventors: Keith F. Anderson, Alex Grichener
  • Patent number: 12313807
    Abstract: A system for detecting forbidden objects worn or carried by individuals includes a metal detector having at least three transducers arranged on either side of a passage, two of these transducers being positioned on the one same side of the passage and spaced apart longitudinally in the direction of travel through the passage, while the third transducer is positioned on the opposite side of the passage so that the three transducers are available in combination to perform spatial discrimination of the location of the metallic objects detected.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: May 27, 2025
    Inventor: Alessandro Manneschi
  • Patent number: 12292455
    Abstract: The present application discloses a chip socket, a testing fixture and a chip testing method thereof. The chip socket includes a pedestal, a plurality of conductive traces, a plurality of clamp structures, and a plurality of electrical contacts. The plurality of conductive traces are formed in the pedestal. The plurality of clamp structures are conductive and disposed on the first surface of the pedestal, and at least one of the plurality of clamp structures is coupled to a corresponding conductive trace and configured to clamp a solder ball of a chip to be tested. The plurality of electrical contacts are disposed on the second surface of the pedestal, and at least one of the plurality of electrical contacts is coupled to a corresponding clamp structure through a corresponding conductive trace.
    Type: Grant
    Filed: February 23, 2024
    Date of Patent: May 6, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shih-Ting Lin
  • Patent number: 12287940
    Abstract: Using a capacitance sensor may include taking a first noise measurement by imposing a first signal on a capacitance sensor, the first signal having a first frequency; taking a second noise measurement by imposing a second signal on the capacitance sensor, the second signal having a second frequency different than the first frequency; determining the measurement with the lower amount of noise between the first noise measurement and the second noise measurement; and taking a capacitance measurement by imposing a third signal on the capacitance sensor, the third signal having either the first frequency or the second frequency based, at least in part, on the frequency of the measurement with the lower amount of noise.
    Type: Grant
    Filed: March 20, 2023
    Date of Patent: April 29, 2025
    Assignee: Cirque Corporation
    Inventor: Brian Monson
  • Patent number: 12276692
    Abstract: A calibration apparatus is provided with a calibration card (6) attachable in an insertion opening (E) of a wafer prober (1) to form a corresponding substantially closed space. A calibration temperature probe (60, 61) attached to the calibration card can be approached by a temperature-controlled chuck (3), for clamping the wafer (4) which can be moved by means of a position controller (350) in lateral directions and in height direction. The position controller operates in such a way that the calibration temperature probe (60, 61) can detect a respective current temperature at various positions on the surface (O) of the chuck or on the surface (O?) of a wafer (4) clamped thereon.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: April 15, 2025
    Assignee: ERS Electronic GmbH
    Inventor: Klemens Reitinger
  • Patent number: 12270863
    Abstract: A non-intrusive, in-situ power method for measuring the loss associated with magnetic components (for example, an inductor) of a power converter is provided. The method involves first capturing a first set of voltage and current waveforms from the power converter. An additional capacitor is then connected to the power converter and a second set of voltage and current waveforms are captured. Based on the first set of waveforms and the second set of waveforms, a timing skew between the current and voltage waveforms captured from the power converter may be determined. This timing skew may then be used to determine the loss of the inductor. The loss may be used to design an optimized power converter.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: April 8, 2025
    Assignee: The Florida State University Research Foundation, Inc.
    Inventors: Jinyeong Moon, Lifang Yi
  • Patent number: 12265146
    Abstract: A calibration circuit may include a calibration signal generator configured to receive an oscillator signal provided by an oscillator and generate a calibration signal based on the oscillator signal. The calibration signal may be generated to have a predetermined amplitude. The calibration circuit may include a calibration peak detector configured to detect a peak amplitude of the calibration signal. The calibration circuit may include a logic circuit configured to calibrate a peak detector connected to the oscillator based at least in part on the peak amplitude of the calibration signal.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: April 1, 2025
    Assignee: Infineon Technologies AG
    Inventors: Giovanni Boi, Fabio Padovan, Luigi Grimaldi, Dmytro Cherniak
  • Patent number: 12259358
    Abstract: The present invention relates to an eddy current sensor for detecting a crack in a battery cell, and a system for detecting a crack of a battery cell including the eddy current sensor. According to the present invention, it is possible to easily detect a crack generated in an electrode, an electrode tab or a welded portion.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: March 25, 2025
    Assignee: LG ENERGY SOLUTION, LTD.
    Inventors: Ji Won Park, Kwang Hyun Kim, Yeon Hyuk Heo, Jae Won Jeong, Eun Gu Han, Min Su Hwang, Myung Han Lee
  • Patent number: 12259451
    Abstract: A nuclear magnetic resonance coil array and a decoupling method thereof, and a nuclear magnetic resonance detection device. The coil array includes: a coil resonant unit and a decoupling network unit, where the coil resonant unit includes multiple coil resonant circuits; the decoupling network unit includes multiple decoupling circuits; where a coil resonant circuit includes a coil and a resonant capacitor; the resonant capacitor in each coil resonant circuit is connected in parallel with the coil; the coils in each coil resonance circuit are equally spaced on a circumference; a decoupling circuit is provided between a positive terminal and a negative terminal of adjacent coils, respectively; each coil is connected to an antenna switching circuit of a nuclear magnetic resonance detection device at the same time.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: March 25, 2025
    Assignee: China University of Petroleum-Beijing
    Inventors: Lizhi Xiao, Sihui Luo, Guangzhi Liao, Zhengduo Wang, Yongheng Fan
  • Patent number: 12253541
    Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system mainly comprises a coolant circulation module, which includes a coolant supply channel communicated with an inlet of a chip socket and a coolant recovery channel communicated with an outlet of the chip socket. When an electronic device is accommodated in the chip socket, the coolant circulation module supplies a coolant into the chip socket through the coolant supply channel and the inlet, and the coolant passes through the pogo pins and then flows into the coolant recovery channel through the outlet.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: March 18, 2025
    Assignee: CHROMA ATE INC.
    Inventors: I-Shih Tseng, Xin-Yi Wu, I-Ching Tsai, Chin-Yi Ouyang
  • Patent number: 12253579
    Abstract: A magnetic sensor includes a magnetic field converter, a magnetic field detector, and a plurality of shields aligned in a Y direction. The magnetic field converter includes a plurality of yokes. Each yoke has a shape elongated in the Y direction, and is configured to receive an input magnetic field component in a direction parallel to a Z direction and to output an output magnetic field component in a direction parallel to an X direction. The magnetic field detector includes a plurality of trains of elements. Each train of elements includes a plurality of MR elements that are aligned in the Y direction along one yoke and connected in series. Each shield has such a shape that its maximum dimension in the Y direction is smaller than its maximum dimension in the X direction.
    Type: Grant
    Filed: January 10, 2024
    Date of Patent: March 18, 2025
    Assignee: TDK CORPORATION
    Inventor: Keisuke Uchida
  • Patent number: 12253560
    Abstract: A tester apparatus is described. Various components contribute to the functionality of the tester apparatus to facilitate movement of a wafer pack holding a vacuum without human oversight. These functionalities include a latch system to keep the wafer pack intact and a pressure sensing system to detect and relay a pressure in the wafer pack.
    Type: Grant
    Filed: September 11, 2024
    Date of Patent: March 18, 2025
    Assignee: AEHR TEST SYSTEMS
    Inventors: Gaylord Lewis Erickson, II, Jovan Jovanovic