Patents Examined by Paresh Patel
  • Patent number: 10067175
    Abstract: Systems and methods of determining bond wire failures are provided. In particular, data indicative of a first resistance of a first bond wire set associated with a first semiconductor device on a power semiconductor module can be obtained. In addition, data indicative of a second resistance of a second bond wire set associated with a second semiconductor device on the power semiconductor module can be obtained. A bond wire failure can then be determined in the first bond wire set or the second bond wire set based at least in part on the data indicative of the first resistance of the first bond wire set and the data indicative of the second resistance of the second bond wire set.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: September 4, 2018
    Assignee: General Electric Company
    Inventors: Juan Diego Ramirez, Robert Gregory Wagoner
  • Patent number: 10060973
    Abstract: Described herein are various technologies pertaining to identifying counterfeit integrated circuits (ICs) by way of allowing the origin of fabrication to be verified. An IC comprises a main circuit and a test circuit that is independent of the main circuit. The test circuit comprises at least one ring oscillator (RO) signal that, when energized, is configured to output a signal that is indicative of a semiconductor fabrication facility where the IC was manufactured.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 28, 2018
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Ryan Helinski, Lyndon G. Pierson, Jr., Edward I. Cole, Jr., Tan Q. Thai
  • Patent number: 10056354
    Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips stacked and packaged therein, wherein each of the semiconductor chips includes: a through-silicon via (TSV) formed through the semiconductor chip; a probe pad exposed to an outside of the semiconductor chip so as to enable a probing test; a bump pad exposed to the outside of the semiconductor chip and electrically connected to the TSV; and a conductive layer electrically connecting the probe pad and the bump pad inside the semiconductor chip.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: August 21, 2018
    Assignee: SK hynix Inc.
    Inventor: Yeon Ok Kim
  • Patent number: 10048335
    Abstract: A specially shaped coil assembly for accurate adjustment of the magic angle is provided to permit accurate adjustment of an angle made between the direction of a static magnetic field and the axis of sample spinning without impairing the resolution of NMR signals. The sample is placed within the external static magnetic field B0. The coil assembly is for use in a solid-state NMR apparatus that performs NMR detection while spinning the sample about an axis tilted at the magic angle relative to the external static magnetic field B0. The coil assembly comprises a pair of arcuate conductor lines and a pair of straight conductor lines. Each of the arcuate lines has a diameter of 2a. Each of the straight lines has a length of 2L. The diameter 2a and the length 2L are so selected as to satisfy the relationship: 1.91?2L/2a?2.15.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 14, 2018
    Assignee: JEOL Ltd.
    Inventors: Tatsuya Matsunaga, Kiyonori Takegoshi, Takashi Mizuno
  • Patent number: 10042002
    Abstract: According to an embodiment, a contact measurement circuit is configured to be coupled between a first contact and a second contact, and the contact measurement circuit includes a first transistor, a control capacitor, and a voltage measurement unit. The first transistor includes a first conduction terminal configured to be coupled to the first contact, a second conduction terminal, and a first control terminal. The control capacitor includes a first capacitor terminal coupled to the second conduction terminal and a second capacitor terminal coupled to the first control terminal. The voltage measurement unit is coupled to the first capacitor terminal and the second capacitor terminal, and the second capacitor terminal is configured to be coupled to the second contact.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: August 7, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Anton Mauder, Jens Barrenscheen
  • Patent number: 10031163
    Abstract: An electrical contact that employs a common compressible layer for all contacts, wherein the compressible layer is fashioned with ducts that contain bridges within them. The bridges are formed of the compressible layer. This bridge serves as a compressible member for a first and second member in electrical contact with each other, and that interact with each other such that a compression force acted on the first and second members will cause them to maintain electrical contact while compressing the bridge. When the compressive force is released, the bridge, acting like a spring, expands thus pushing the first and second members apart, but still in electrical contact with each other.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: July 24, 2018
    Assignee: JF MICROTECHNOLOGY SDN. BHD.
    Inventors: Wei Kuong Foong, Kok Sing Goh, Shamal Mundiyath, Eng Kiat Lee
  • Patent number: 10018745
    Abstract: A method for monitoring a primary field dipole moment in a TDEM geological surveying system, including measuring a sign and amplitude of a primary field generated by a transmitter loop and sensed by a receiver in each of a plurality of sensitive axes, and in dependence thereon calculating a vector which represents orientation of the primary field at the receiver location in a receiver frame of reference; and determining, in dependence on the vector an orientation of the primary field dipole moment in a receiver frame of reference.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: July 10, 2018
    Assignee: GEOTECH LTD.
    Inventor: Jack Dodds
  • Patent number: 10019955
    Abstract: The invention discloses an array substrate, a display panel and a display device, and belongs to the field of array substrate test technology, which can solve the problem that the performance of the thin film transistor at the display region of the array substrate in an ADS mode cannot be accurately tested. The array substrate in the invention comprises a plurality of pixel units, each of which comprises a pixel electrode, an insulating layer above the pixel electrode, and a common electrode above the insulating layer, wherein at least one of the pixel units is a test pixel unit, wherein an opening is provided in the insulating layer of the test pixel unit to be above the pixel electrode and separated from the common electrode. The display panel and the display device in the invention comprise the above array substrate.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: July 10, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ziwei Cui, Hongjun Yu, Hong Zhu, Hao Wu
  • Patent number: 10006938
    Abstract: The elongated body of an electrically conductive contact probe can be disposed in a guide hole and can include a patterned region for engaging and riding on a contact region of an inner sidewall of the guide hole as the elongated body moves in the guide hole in response to a force on a tip of the probe. As the patterned region rides the contact region, the tip moves in a lateral pattern that is a function of the surface(s) of the patterned region.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: June 26, 2018
    Assignee: FormFactor, Inc.
    Inventors: Keith J. Breinlinger, Kevin J. Hughes, Russell Newstrom
  • Patent number: 10006939
    Abstract: Testing probe and semiconductor testing fixture, and their fabrication methods are provided. A testing probe may configure a chamber through an insulating body. A first testing pin is disposed inside the chamber of the insulating body. The first testing pin includes: a first testing terminal on one end of the first testing pin and a first connection terminal on another end of the first testing pin. An elastic member is disposed inside the chamber and attached to the first testing pin to drive an upward or downward movement of the first testing pin along the chamber. A second testing pin is disposed around an outer sidewall surface of the insulating body enclosing the first testing pin. The second testing pin includes a second testing terminal on one end of the second testing pin and a second connection terminal on another end of the second testing pin.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: June 26, 2018
    Assignee: TONGFU MICROELECTRONICS CO., LTD.
    Inventor: Lei Shi
  • Patent number: 10001449
    Abstract: Systems, methods, and test kits for detecting and quantifying an analyte level in a biological fluid sample using impedance measurements, are disclosed. The fluid sample is applied to a lateral flow strip, and impedance of the strip is measured as the assay dries. Analysis of the drying-dependent impedance measurements indicates the presence and quantity of the analyte in the fluid sample.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: June 19, 2018
    Assignee: Church & Dwight Co., Inc.
    Inventors: Albert Nazareth, Shang Li, Timothy Snowden, Giles H. W. Sanders, Anthony Cass
  • Patent number: 10001520
    Abstract: A method of testing an insulation system is disclosed. The method comprises coupling a first test lead to a first conductor, the first conductor at least partly isolated by the insulation system and coupling a second test lead to a second conductor or a ground. The method further comprises applying a test signal to the first test lead, receiving a test response from the second test lead, and analyzing the test response from the second test lead to determine a harmonic content of the test response. The method further comprises, when the harmonic content is equal to or greater than a predetermined threshold, determining that the insulator system has non-linear properties.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: June 19, 2018
    Assignee: AVO Multi-Amp Corporation
    Inventors: Nils Peter Werelius, Mats Gunnar Ohlen
  • Patent number: 9989583
    Abstract: A cross-bar unit for a test apparatus for circuit boards having at least one cross-bar spanning a test field in which a circuit board to be tested may be placed, and is configured to hold positioning units for test fingers in a linearly traversable manner so that the test fingers are able to scan at least part of the test field. The cross-bar unit is configured to hold at least two linear guides, independent of one another, for guiding in each case at least one of the positioning units.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: June 5, 2018
    Assignee: Xcerra Corporation
    Inventors: Victor Romanov, Bernd-Ulrich Ott
  • Patent number: 9983231
    Abstract: A multipoint probe for establishing an electrical connection between a test apparatus and a test sample, the multipoint probe comprising a base defining a top surface and a plurality of traces provided on the top surface, each trace individually interconnecting a contact pad and a contact electrode for establishing the electrical connection to the test sample, each trace comprising a wide portion connected to the contact pad and a narrow portion connected to the contact electrode; the first top surface comprising first intermediate surfaces, each interconnecting a pair of neighboring traces at their respective wide portions, and second intermediate surfaces, each interconnecting a pair of neighboring traces at their respective narrow portions, and the first intermediate surfaces being provided on a first level and the second intermediate surfaces being provided on a second level above the first level relative to the base.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: May 29, 2018
    Assignee: CAPRES A/S
    Inventor: Lior Shiv
  • Patent number: 9977093
    Abstract: An electronic apparatus includes: an internal power supply to be charged; a charging circuit configured to supply electrical power from an external power supply to the internal power supply; a voltage measurement circuit configured to measure a voltage of the internal power supply; a temperature sensor configured to measure a temperature of the internal power supply; and an estimation circuit configured to estimate a degree of degradation of the internal power supply, wherein the estimation circuit determines whether it is possible to perform a degradation estimation process to estimate the degree of degradation of the internal power supply based on the voltage of the internal power supply and the temperature of the internal power supply, and performs the degradation estimation process on the internal power supply only when determining that it is possible to perform the degradation estimation process on the internal power supply.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 22, 2018
    Assignee: KONICA MINOLTA, INC.
    Inventors: Yuki Ikeda, Yoshihiko Eguchi
  • Patent number: 9977053
    Abstract: A wafer probe alignment system and method for aligning a probe to a chip wafer for testing a chip on the wafer are provided. At least two corners of the probe are adjustable in a same direction in relation to a primary corner of the probe. The alignment approach includes providing a grid of signal pins for corresponding contact pads of the chip under test, determining for each signal pin whether an electrical contact is established to a corresponding contact pad of the chip under contact force, and adjusting a position of each of the at least two corners by a corner individual delta position value with respect to the direction depending on a result of the determining in order to establish an electrical contact between each of the pins and the corresponding contact pads of the chip under test.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 22, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joerg G. Appinger, Eberhard Dengler, Roland Dieterle, Martin Eckert, Gabriele Kuczera, Siegfried Tomaschko, Otto Torreiter, Quintino Lorenzo Trianni
  • Patent number: 9952279
    Abstract: A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mill-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Hao Chen, Chung-Han Huang, Chung-Sheng Yuan, Ching-Fang Chen, Wen-Wen Hsieh, Meng-Lin Chung
  • Patent number: 9952280
    Abstract: An electronic device with COF package is provided. The electronic device includes a flexible substrate, a core circuit unit, multiple output pads and multiple switching elements. First terminals of the switching elements are respectively and electrically connected to output pads of the core circuit unit, and second terminals of the switching elements are respectively and electrically connected to the output pads. In a test stage of the electronic device, the switching elements are sequentially turned on such that one of multiple output signals of the core circuit unit is transmitted to a common test pad outside of the electronic device through corresponding one of the output pads.
    Type: Grant
    Filed: June 12, 2016
    Date of Patent: April 24, 2018
    Assignee: Novatek Microelectronics Corp.
    Inventor: Jhih-Siou Cheng
  • Patent number: 9949683
    Abstract: A method is provided for making multiple environmental measurements using a single sensing element. Each sensing element (sensel) includes a thin-film transistor (TFT) and a passive element. Typically, a plurality of sensels is provided arranged into an array. In response to an electrical stimulus, an electrical measurement is supplied that is responsive to a change in TFT electrical characteristic correlated to a first environmental condition, as well as a change in a characteristic of the passive element correlated to a second environmental condition. When the sensels are formed in an array, a plurality of electrical measurements is supplied corresponding plurality of locations on a monitored surface. Some exemplary environmental conditions include temperature, pressure, moisture, chemicals, oxygen, solution pH, salinity, and shear.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 24, 2018
    Assignee: Sharp Laboratories of America, Inc.
    Inventor: Themistokles Afentakis
  • Patent number: 9952277
    Abstract: A test device uses a single probe to test plurality of pads of at least one chip, and includes a test circuit, a plurality of short-circuit elements and a plurality of probes. The plurality of short-circuit elements is formed in scribe lines around the at least one chip, where each of the plurality of short-circuit elements connects the plurality of pads, and the plurality of pads includes one testing pad and at least one non-testing pad. The plurality of probes receives a plurality of test signals generated by the at least one chip from the testing pad via the plurality of short-circuit elements, so the test circuit generates a test result according to the plurality of test signals.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 24, 2018
    Assignee: SYNC-TECH SYSTEM CORP.
    Inventors: Hung-Wei Lai, Tsung-Jun Lee