Patents Examined by Patricia A. George
  • Patent number: 7407596
    Abstract: A fluxgate sensor is integrated in a printed circuit board. The fluxgate sensor has two bar-type (or rectangular-ring shaped) soft magnetic cores to form a closed magnetic path on a printed circuit board and an excitation coil in the form of a metal film is wound around the two bar-type soft magnetic cores either in a united structure that winds the two bar-type soft magnetic cores altogether, or in a separated structure that winds the two bar-type soft magnetic cores respectively, both in a pattern of number ‘8’. A pick-up coil is mounted on the excitation coil, either winding the two bars altogether, or respectively, in a solenoid pattern. The fluxgate sensor integrated in the printed circuit board can be mass-produced at a cheap manufacturing cost. The fluxgate sensor also can be made compact-sized, and at the same time, is capable of forming a closed-magnetic path.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: August 5, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Won-youl Choi, Byeong-cheon Koh, Kyung-won Na, Sang-on Choi, Myung-sam Kang, Keon-yang Park
  • Patent number: 7402526
    Abstract: A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least two regions that exhibit different plasma densities. The method includes exposing at least some of the surface to both of the at least two regions. Exposing the surface to both of the at least two regions may include rotating the plasma and may cyclically expose the surface to the plasma density differences. Exposing to both of the at least two regions may modify a composition and/or structure of the surface. The plasma may include a plasmoid characterized by a steady state plasma wave providing multiple plasma density lobes uniformly distributed about an axis of symmetry and providing plasma between the lobes exhibiting lower plasma densities. Depositing the layer can include ALD and exposure may remove an ALD precursor ligand.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: July 22, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Neal R. Rueger
  • Patent number: 7396480
    Abstract: A method for removing native oxides from a substrate surface is provided. In at least one embodiment, the method includes supporting the substrate surface in a vacuum chamber and generating reactive species from a gas mixture within the chamber. The substrate surface is then cooled within the chamber and the reactive species are directed to the cooled substrate surface to react with the native oxides thereon and form a film on the substrate surface. The substrate surface is then heated within the chamber to vaporize the film.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: July 8, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Chien-Teh Kao, Jing-Pei (Connie) Chou, Chiukin (Steven) Lai, Sal Umotoy, Joel M. Huston, Son Trinh, Mei Chang, Xiaoxiong (John) Yuan, Yu Chang, Xinliang Lu, Wei W. Wang, See-Eng Phan
  • Patent number: 7393460
    Abstract: The plasma processing method comprises the step of removing an organic material film forming an upper layer relative to a patterned SiOCH series film by the processing with a plasma of a process gas containing an O2 gas, wherein the plasma has an O2+ ion density not lower than 1×1011 cm?3 and an oxygen radical density not higher than 1×1014 cm?3.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: July 1, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Masaru Hori, Kazuhiro Kubota
  • Patent number: 7390745
    Abstract: A method for producing predetermined shapes in a crystalline Si-containing material that have substantially uniform straight sides or edges and well-defined inside and outside corners is provided together with the structure that is formed utilizing the method of the present invention. The inventive method utilizes conventional photolithography and etching to transfer a pattern, i.e., shape, to a crystalline Si-containing material. Since conventional processing is used, the patterns have the inherent limitations of rounded corners. A selective etching process utilizing a solution of diluted ammonium hydroxide is used to eliminate the rounded corners providing a final shape that has substantially straight sides or edges and substantially rounded corners.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: June 24, 2008
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Kenneth T. Settlemyer, Jr., James J. Toomey, Haining Yang
  • Patent number: 7378346
    Abstract: A method is provided for forming a monolithically integrated optical filter, for example, a Fabry-Perot filter, over a substrate (10). The method comprises forming a first mirror (16) over the substrate (10). A plurality of etalon material layers (32, 34, 36, 38) are formed over the mirror (16), and a plurality of etch stop layers (42, 44, 46) are formed, one each between adjacent etalon material layers (32, 34, 36, 38). A photoresist is patterned to create an opening (54) over the top etalon material layer (38) and an etch (56) is performed down to the top etch stop layer (46). An oxygen plasma (58) may be applied to convert the etch stop layer (46) within the opening (54) to silicon dioxide (57). The photoresist patterning, etching, and applying of an oxygen plasma may be repeated as desired to obtain the desired number of levels (82, 84, 86, 88). A second mirror (72) is then formed on each of the levels (82, 84, 86, 88).
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: May 27, 2008
    Assignee: Motorola, Inc.
    Inventors: Ngoc V. Le, Jeffrey H. Baker, Diana J. Convey, Paige M. Holm, Steven M. Smith
  • Patent number: 7368064
    Abstract: A method of manufacturing a semiconductor device forms an interlayer insulating film on a nickel silicide layer formed on a substrate, and forms a through hole by performing dry etching using a resist pattern, formed on the interlayer insulating film, as a mask and then removing the resist pattern by ashing. A wafer after an ashing process is cleaned using a cleaning solution comprised of aqueous solution having a content of the fluorine-containing compound of 1.0 to 5.0 mass %, a content of chelating agent of 0.2 to 5.0 mass %, and a content of the organic acid salt of 0.1 to 3.0 mass %.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: May 6, 2008
    Assignees: NEC Electronics Corporation, Kanto Kagaku Kabushiki Kaisha
    Inventors: Hidemitsu Aoki, Tatsuya Suzuki, Takuo Ohwada, Kaoru Ikegami, Norio Ishikawa
  • Patent number: 7368062
    Abstract: Undoped layers are introduced in the passive waveguide section of a butt-joined passive waveguide connected to an active structure. This reduces the parasitic capacitance of the structure.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: May 6, 2008
    Assignee: Avago Technologies Fiber IP Pte Ltd
    Inventors: Tirumala R. Ranganath, Jintian Zhu
  • Patent number: 7368394
    Abstract: Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: May 6, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Meihua Shen, Uwe Leucke, Guangxiang Jin, Xikun Wang, Wei Liu, Scott Williams
  • Patent number: 7361285
    Abstract: A method for fabricating a cliché including: providing a transparent glass substrate; depositing a metal layer on the substrate; patterning the metal layer and thereby forming a first metal pattern; etching the glass substrate by using the first metal pattern as a mask and thereby forming a first convex pattern; patterning the first metal pattern and thereby forming a second metal pattern; and etching the first convex pattern by using the second metal pattern as a mask and thereby forming a second convex pattern.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: April 22, 2008
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Chul-Ho Kim
  • Patent number: 7361286
    Abstract: A method of detecting an etching end-point includes the steps of: forming a mask on a pattern area of an etching object; forming an etching indicator on an etching area of the etching object, which is not covered by the mask; etching the etching object using the mask; and evaluating the size of a remaining object covered by the mask using the etching indicator.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: April 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hyun Kim, Yu-Dong Bae, Jung-Kee Lee, In Kim
  • Patent number: 7361604
    Abstract: A semiconductor manufacturing method that includes depositing a first layer over a substrate, providing a layer of hardmask over the first layer, patterning and defining the hardmask layer to form at least two hardmask structures, wherein each hardmask structure includes at least one substantially vertical sidewall and one substantially horizontal top, and wherein the hardmask structures are separated by a first space, depositing a photo-insensitive material over the at least two hardmask structures and the first layer, wherein an amount of the photo-insensitive material deposited on the top of the hardmask structures is substantially greater than an amount of the photo-insensitive material deposited on the at least one sidewall of the hardmask structures, wherein the hardmask structures with the photo-insensitive layer on the sidewalls thereof are separated by a second space, and wherein the first space is greater than the second space.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: April 22, 2008
    Assignee: Macronix International Co., Ltd.
    Inventors: Henry Wei-Ming Chung, Shin-Yi Tsai, Ming-Chung Liang
  • Patent number: 7358192
    Abstract: Embodiments of a cluster tool, processing chamber and method for processing a film stack are provided. In one embodiment, a method for in-situ etching of silicon and metal layers of a film stack is provided that includes the steps of etching an upper metal layer of the film stack in a processing chamber to expose a portion of an underlying silicon layer, and etching a trench in the silicon layer without removing the substrate from the processing chamber. The invention is particularly useful for thin film transistor fabrication for flat panel displays.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: April 15, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Walter R. Merry, Quanyuan Shang, John M. White
  • Patent number: 7358190
    Abstract: Methods of forming material in a gap in a substrate include forming a pattern to define a gap on a substrate. A bottom oxide layer is formed on a surface of the substrate and substantially filling the gap. The bottom oxide layer is etched back inside an opening in the gap to expose side walls of the gap so that a residual bottom oxide layer remains at a bottom of the gap. A top oxide layer is selectively deposited on the residual bottom oxide layer, wherein the top oxide layer is deposited in a first direction toward the opening at a faster rate than in a second direction away from the side walls.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: April 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-gun Kim, Kyu-tae Na, Eun-Kee Hong, Ju-Seon Goo
  • Patent number: 7358193
    Abstract: A vacuum chamber includes a plasma generating space in its interior. A magnetic field generating device applies a fluctuating magnetic field to the plasma generating space to cause plasma therein to fluctuate. A substrate is placed in the plasma generating space so that when a potential difference is evoked between a first conductor and a second conductor as a result of the fluctuation of the plasma, the potential difference causes nanoholes to be formed in the substrate.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: April 15, 2008
    Assignee: TDK Corporation
    Inventors: Junichi Sato, Hajime Amano, Fujimi Kimura
  • Patent number: 7351347
    Abstract: GaN crystal having few dislocations is grown by using together ELO-mask and defect-seeding-mask means. ELO masks make it so that GaN crystal does not grow directly, but grows laterally; defect-seeding masks make it so that closed defect-gathering regions in which defects are concentrated are grown. Any of the materials SiN, SiON or SiO2 is utilized for the ELO mask, while any of the materials Pt, Ni or Ti is utilized for the defect-seeding masks. With a sapphire, GaAs, spinel, Si, InP, SiC, etc. single-crystal substrate, or one in which a GaN buffer layer is coated onto a single-crystal substrate of these, as an under-substrate, the ELO mask and defect-seeding masks are provided complementarily and GaN is vapor-phase deposited.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: April 1, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takuji Okahisa
  • Patent number: 7351354
    Abstract: A removing solution for removing tungsten metal which causes a film formation on a semiconductor substrate or adheres to it, wherein orthoperiodic acid and water are contained.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: April 1, 2008
    Assignee: Kanto Kagaku Kabushiki Kaisha
    Inventors: Toshikazu Shimizu, Kaori Watanabe, Hidemitsu Aoki
  • Patent number: 7348276
    Abstract: A method of fabricating a semiconductor device includes a polishing process of a substrate, wherein the polishing process includes the steps of applying a chemical mechanical polishing process to the substrate on a polishing pad while using slurry, and conditions a surface of the polishing pad, the conditioning step including the step of grinding the surface of said polishing pad by at least first and second conditioning disks of respective, different surface states.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: March 25, 2008
    Assignee: Fujitsu, Limited
    Inventor: Tetsuya Shirasu
  • Patent number: 7335597
    Abstract: To realize the reduction of a manufacturing cost and the enhancement of yield by reducing the number of steps of a TFT in an electro-optical device typified by an active matrix liquid crystal display device. A semiconductor device of the present invention is characterized by including a first wiring and a second wiring formed of a first conductive film on the same insulating surface, a first semiconductor film of one conductivity type formed on the first and second wirings so as to correspond thereto, a second semiconductor film formed on an upper layer of the first semiconductor film of one conductivity type across the first wiring and the second wiring, an insulating film formed on the second semiconductor film, and a third conductive film formed on the insulating film.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: February 26, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Arao, Hideomi Suzawa
  • Patent number: 7329364
    Abstract: A method for manufacturing a bonded wafer with ultra-thin single crystal ferroelectric film is provided, comprising the following steps: providing a single crystal ferroelectric wafer and a carrier wafer while activating the surfaces of the single crystal ferroelectric wafer and the carrier wafer; bonding the activated surface of the single crystal ferroelectric wafer to the activated surface of the carrier wafer; and thinning the single crystal ferroelectric wafer for forming an ultra-thin single crystal ferroelectric film. Wherein, the thinning process in the aforesaid preferred embodiment is the method of polishing, grinding, chemical mechanical polishing, or etching. And the bonding force generated in the bonding process is strong enough to resist the shearing force.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: February 12, 2008
    Assignee: Industrial Technology Research Institute
    Inventors: Shih-Shian Ho, Hung-Yin Tsai, Chia-Jen Ting, Chun-Fa Lan, Chii-Chang Chen