Abstract: This invention relates to the manufacture of dual damascene interconnect structures in integrated circuit devices. Specifically, a method is disclosed for forming a single or dual damascene structure in a low-k dielectric thin film utilizing a planarizing material and a compressive diffusion barrier material. The barrier material preferably has a compressive stress of greater than 300 MPa. In a preferred dual damascene embodiment of this method, the vias are formed first in the dielectric material, then the planarizing material is deposited in the vias and on the dielectric material, and the barrier material is deposited on the planarizing material. The trenches are then formed lithographically in the imaging material, etched through the barrier material into the planarizing material, and the trench pattern is transferred to the dielectric material. During and following the course of these etch steps, the imaging, barrier and planarizing materials are removed.

Abstract: A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, performing a process to increase a wet etch rate of a remaining portion of the conductive layer, and forming a conductive layer pattern by wet etching the remaining portion of the conductive layer after performing the plasma process or the ion implantation. The process to increase the wet etch rate of the conductive layer including a plasma process and/or an ion implantation on the remaining portion of the conductive layer.

Abstract: A method is provided that includes a main laminate making step of forming a plurality of main magnetic poles onto a substrate, covering each magnetic pole with a first protective film, and forming onto the first protective film a stopper film provided with openings at respective parts opposing the main magnetic poles. Each opening is wider than a planar width of a corresponding main magnetic pole, so as to make a main laminate. The method includes a main polishing step of polishing the first protective film and main magnetic poles through the openings of the stopper film in the main laminate by a CMP method. In the main laminate making step, the openings in the stopper film is provided with a width distribution.

Abstract: A flash memory and a fabrication method thereof, which is capable of improving a whole capacitance of the flash memory by forming a tunneling oxide and a floating gate only in a portion where injection of electrons occurs. A flash memory wherein a tunneling oxide and a floating gate are formed only in a portion where injection of electrons occurs and a gate insulation film is formed on a semiconductor substrate between two portions of the tunneling oxide.

Abstract: A method for treating a gate structure comprising a high-K gate dielectric stack to improve electric performance characteristics including providing a gate dielectric layer stack including a binary oxide over a silicon substrate; forming a polysilicon layer over the gate dielectric layer stack; lithographically patterning and etching to form a gate structure; and, carrying out at least one plasma treatment of the gate structure comprising a plasma source gas selected from the group consisting of H2, N2, O2, and NH3.

Abstract: In a method for forming microlenses, an etching process is performed by using a processing gas on an object to be processed provided with a substrate, a lens material layer formed on the substrate and a mask layer of a lens shape formed on the lens material layer to etch the lens material layer and the mask layer, so that the lens shape of the mask layer is transcribed to the lens material layer. The processing gas is a gaseous mixture of a gas containing fluorine atoms but no carbon atoms and a fluorocarbon-based gas having a ratio of the number of carbon atoms to the number of fluorine atoms which is greater than or equal to 0.5, the gaseous mixture having no oxygen gas.

Abstract: A method of forming a fine pattern by a tri-layer resist process to overcome a bi-layer resist process is disclosed. When a fine pattern is formed using a silicon photoresist, a gas protection film is coated on a photoresist to prevent exhaustion of silicon gas generated from the photoresist in light examination of high energy. As a result, lens of exposure equipment may be prevented from being contaminated.

Abstract: A method for chemical mechanical polishing of semiconductor substrates containing a metal layer requiring removal and metal interconnects utilizing a composition containing engineered copolymer molecules comprising hydrophilic functional groups and relatively less hydrophilic functional groups; the engineered copolymer molecules enabling contact-mediated reactions between the polishing pad surface and the substrate surface during CMP resulting in minimal dishing of the metal interconnects in the substrate.

Abstract: An aqueous chemical mechanical planarizing composition includes an oxidizer for promoting barrier removal and an abrasive. Inhibitor decreases removals of a metal interconnect. The composition has a carboxylic acid polymer having at least one repeat unit of the polymer comprising at least two carboxylic acid functionalities, a pH of less than or equal to 4 and a tantalum nitride removal rate of at least eighty percent of copper removal rate at a pad pressure of 13.8 kPa.

Abstract: An etching method for plasma-etching a low-k film, wherein the plasma etching is conducted under an etching gas atmosphere including a fluorocarbon gas, O2 gas and Ar gas, and under the conditions of a pressure of 60 mTorr (7999.32 mPa) or higher and a high-frequency output (RF power) of 600 W or less.

Abstract: A shallow trench isolation (STI) multistage chemical mechanical polishing (CMP) method for forming a shallow trench isolation structure is provided. The substrate comprising a dense region and an isolation region, a silicon nitride layer formed over the substrate, a plurality of trenches formed in the silicon nitride layer and the substrate, an oxide layer formed over the substrate, filling the trenches, wherein a width of the trenches in the dense region is smaller than that in the isolation region. A first polishing step is performed to remove a portion of the silicon oxide layer until a thickness of the remaining portion of the oxide layer reaches a predetermined thickness. A second polishing step is performed to remove a portion of the remaining portion of the silicon oxide layer until the silicon nitride layer is exposed.

Abstract: The present invention provides a method for polishing silica and silicon nitride on a semiconductor wafer comprising the steps of planarizing the silica with a first aqueous composition comprising by weight percent 0.01 to 5 carboxylic acid polymer, 0.02 to 6 abrasive, 0.01 to 10 polyvinylpyrrolidone, 0 to 5 cationic compound, 0 to 1 phthalic acid and salts, 0 to 5 zwitterionic compound and balance water, wherein the polyvinylpyrrolidone has an average molecular weight between 100 grams/mole to 1,000,000 grams/mole. The method further provides detecting an endpoint to the planarization, and clearing the silica with a second aqueous composition comprising by weight percent 0.001 to 1 quaternary ammonium compound, 0.001 to 1 phthalic acid and salts thereof, 0.01 to 5 carboxylic acid polymer, 0.01 to 5 abrasive and balance water.

Abstract: A combined wet etching method for stacked films which is capable of performing etching processes in a collective manner while controlling an amount of side-etching on each of stacked films and of making uniform side edges. In the wet etching method, two or more types of etching methods are performed in combination, on stacked films containing first and second films being deposited sequentially on a substrate and each having a different film property. The two or more types of wet etching methods include, at least, a first wet etching method in which side-etching on the first film is facilitated more than side-etching on the second film and a second wet etching method in which side-etching on the second film is facilitated more than side-etching on the first film.

Abstract: Spacers are formed on sidewalls of striplike parts of a pattern layer of periodic structure. The pattern layer is removed, and the spacers are covered with a further spacer layer, which is then structured to second sidewall spacers. Gaps between the spacers are filled with a complementary layer. The upper surface is planarized to a lower surface level, leaving a periodic succession of the first spacers, the second spacers and the residual parts of the complementary layer. The lateral dimensions are adapted in such a manner that a removal of one or two of the remaining layers renders a periodic pattern of smaller pitch.

Abstract: A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

Abstract: A method is described for thin film processing using a selected CMP slurry with a silicon dioxide stop layer. The slurry includes an abrasive, preferably alumina, a corrosion inhibitor, preferably benzotriazole (BTA), and an oxidizer preferably hydrogen peroxide. The method is particularly useful for fabricating thin film heads where alumina is used as the dielectric. The method can be used to planarize metal structures surrounded by alumina in magnetic heads. The alumina refill is deposited to the final target height which is slightly below the height of the metal. A thin silicon dioxide stop layer is deposited over the alumina. The CMP is executed using the selected slurry to planarize the wafer down to the stop layer. Preferably only a negligible amount of the stop layer remains and the height of the metal structure is essentially the same as the deposited height of the refilled alumina.

Abstract: A method for forming a pattern is provided that includes: providing a cliché having a plurality of convex patterns; applying an adhesive force reinforcing agent onto each surface of the convex patterns; forming an etching object layer on a substrate and then applying ink onto an upper portion of the etching object layer; attaching the cliché and the substrate to each other such that the convex patterns onto which the adhesive force reinforcing agent is applied can come in contact with the ink applied onto the etching object layer; and forming ink patterns which selectively remain on the etching object layer by separating the substrate and the cliché from each other.

Abstract: Compositions and methods for planarizing or polishing a surface, particularly a semiconductor wafer surface. The polishing compositions described herein comprise (a) a liquid carrier; (b) purified clay; and optional additives, such as (c) a chemical accelerator; and (d) a complexing or coupling agent capable of chemically or ionically complexing with, or coupling to, the metal and/or insulating material removed during the polishing process. The complexing or coupling agent carries away the removed metal and/or silicon dioxide insulator particles, during polishing, to prevent the separated particles from returning to the surface from which they were removed. Also disclosed are methods of planarizing or polishing a surface comprising contacting the surface with the compositions.

Abstract: Disclosed is a method of selectively etching nitride in a chemical downstream etching process. The invention begins by placing a wafer having oxide regions and nitride regions in a chamber. Then, the invention performs a chemical downstream etching process using CH2F2 to etch and convert the nitride regions into surface mediated uniform reactive film (SMURF) regions comprising (NH4)2SiF6. This process then rinses the surface of the wafer with water to remove the surface mediated uniform reactive film regions from the wafer, leaving the oxide regions substantially unaffected. The chemical downstream etching process is considered selective because it etches the nitride regions at a higher rate than the oxide regions.

Abstract: A semiconductor based structure containing substantially smoothed waveguides having a rounded surface is disclosed, as well as methods of fabricating such a structure. The substantially smoothed waveguides may be formed of waveguide materials such as amorphous silicon or stoichiometric silicon nitride. The substantially smoothed waveguides are formed with an isotropic wet etch combined with sonic energy.